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A complet Xilinx Coolrunner CPLD development kit:
Over a true 1284 transciever, configure the onboard XCR3128XL CPLD and
control your new configuration truth an SPP, EPP or ECP dialog. Coming with
complet VHDL example of an active I2C Master Controler over EPP dialog !
An universal JTAG Emulator on your parallel port:
Amontec Team uses the power of the Programmable Logic to emulate all popular
JTAG cables on the Chameleon POD:
RAVEN JTAG Emulator : for all ARM7 ARM9 PPC A7 TRISCEND ...
WIGGLER JTAG Cable : for all ARM7 ARM9 PPC A7 TRISCEND ...
XILINX ParallelCable III : for all Xilinx FPGA Virtex Spartan Coolrunner ...
@ltera ByteBlaster : for all @ltera FPGA
Atmel STK200 : for all AVR processors
Amontec Team offers the Chameleon POD for US149$. ALL JTAG EMULATOR
Configurations are comming for FREE and can be downloaded online!
can you please post/pm me with the actual VDHL or VERILOG code that it comes with for emulating a raven. then i can read it and reverse-engineer some schematics...
btw if you just need a jtag debugger, try the wiggler, also be macraigor. schematics have been posted here before.
the JTAG signals should be available on the front pins of the chameleon. i don't have one so i don't know the specifics.
According the documentation, the cable is the same for Raven and Wiggler mode.
So just config it to wiggler mode and check the signallinks to the 2. sub-d connector according the schematics of wiggler, which can be downloaded everywhere.
Please send me your results The HW seams to be very easy to rebuild.
thanks a lot.
Now only some information about the RAVEN code could be useful for me.
The other configuration are already available by schematic for single solutions.
I think on a new PLD solution with an other (better) PLD, than the Coolrunner, which allow to solve the levelshift problem on a very simple way.
The Lattice ISPMACH4000 family is available with different core voltage levels. But the best is, there are 2 or more Blocks which are hotplugable and they can be supplied with different voltage-levels
So Core via LDO on best 1,8V Core Zero Power version.
1 Block and Jtag switchable to the Parallelport.
A second block to the Jtagside, which is supplied by the target supply voltage.
Levelshift solved And there is no Poweup-Sequencing requirement by the PLD!!
Can anybody share configuration files and coresponding pinout for ChameleonPOD? Friend buy ChemeleonPOD from second hand and Information on www.amontec.com incomplete and Amontec refuse help :-( :-(
I know somebody who have used my idea to rebuild a more optimized version of the Chameleon Pod with the Lattice PLD. By my self i haven't had enough time for this.
Best is, there is no additional power supply used.
At moment he works on the R@VEN Protocol.
I will give you more information if he succeed.
Maybe also you can help a little bit. There are some free tools, which are available in source, where can use the R@VEN or the Chameleon for debugging.
Take a look inside the code and you can see how the data is parallel written to the PLD and seriel shifted out of it.
Maybe also you can help a little bit. There are some free tools, which are available in source, where can use the R@VEN or the Chameleon for debugging.
Can anybody share detail image (foto) of Chameleon POD???
I made clone, but i havent original and somebody connections betven CPLD pins missing and is realy hard is determining. Can anybody help me, please
Can anybody share detail image (foto) of Chameleon POD???
I made clone, but i havent original and somebody connections betven CPLD pins missing and is realy hard is determining. Can anybody help me, please
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The HW seams to be very easy to rebuild.