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    dual supply opamp null

    Hello friends
    I have a problem in a PLL. I have used a loop filter as shown in this figure:

    But the output spectrum is as shown in this figure:

    What's the problem? How I can eliminate the spurs? Pls hlp me.

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    freddy pll

    Quote Originally Posted by elec350
    Hello friends
    I have a problem in a PLL. I have used a loop filter as shown in this figure:

    But the output spectrum is as shown in this figure:

    What's the problem? How I can eliminate the spurs? Pls hlp me.
    With little information, these look like reference spurs, my guess is that the op-amp bias current is the problem. It looks as if you are using ADIsimPLL, try setting the bias current for the op-amp to correspond to your part and see what happens. Alternatively, connect a pot from V+ to ground and a large resistor (say 10M) to the charge pump output and see if you can null out the reference spurs. This will point you in the right direction.


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    •   Alt12th May 2009, 04:32

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    adf4156 spurs

    Hello Fred23;
    Can you explain more? Can you sketch a schematic for me?



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    adisimpll sweep

    Insufficient data given, can not know much unless you tell us the VCO tuning gain, the phase detector gain, and the divisor ratios/frationality. Phase Loked Loops (PLL) are a little complicated. It could be a couple of things:

    1) too wide a loop bandwidth. (or another way of saying it, not enough lowpass filtering in the loop filter)
    2) Marginally stable control loop, so that a little bit of reference spur energy is "ringing" and causing a lot of trouble
    3) External noise, like from a noisy switching voltage regulator
    4) Are you sure it is "phase locked". (if you vary the reference frequency 100 Hz, does the VCO frequency vary by 100 Hz * N exactly?)

    Is the spacing of the spurs mathematically related to the reference frequency used? If you vary R4 up and down, what happens to the spur level in dBc, and does the spacing of the spurs in frequency change?

    Rich
    Last edited by keith1200rs; 1st May 2012 at 09:46. Reason: Advertising removed


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    Re: PLL Problem [pls hlp me]

    Quote Originally Posted by elec350
    Hello Fred23;
    Can you explain more? Can you sketch a schematic for me?
    elec350,

    I'm guessing but these look as if you have a phase detector frequency of 50kHz. If so then they are probably reference spurs. A likely source of these is if the pll locks with a phase offset, in this case the PD puts out small current pulses each 1/50kHz, which if not attenuated sufficiently by the loop filter cause sidebands at 50kHz and harmonics. A possible source is the op amp bias current, you haven't stated what op amp you are using, look at the spec sheet and find out the bias current. Use ADIsimPLL to see if that causes ref spurs that are similar to those you see.

    What is the op amp?


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    Re: PLL Problem [pls hlp me]

    Hello fred23 and biff44
    I have used ADF4156 and ADF4106 as PLL ICs. I have connected tantalum caps from Vcc line of VCO to gnd and spur rejection bacame better. also I have selected narrower loop filter and spur rejection bacame better too. But the lock time became longer. Is there any other way to reject spurs more? (The spur rejection is about 50dBc now).pls hlp.



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    Re: PLL Problem [pls hlp me]

    That is nice, but you are not necessarily converging on a solution.

    Did you inject +/- current into the amp's + terminal, like fred suggested, and what happened? Were you able to null out the spurs at some potentionmeter setting? You could have leaky caps or a poor amp input offset current.

    If you do not care about phase noise, the Analog Devices chip can dither the fractionality to lower the spur level with broadband loop filters.

    RIch
    Last edited by keith1200rs; 1st May 2012 at 09:47. Reason: Advertising removed


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    Re: PLL Problem [pls hlp me]

    Quote Originally Posted by elec350
    Hello fred23 and biff44
    I have used ADF4156 and ADF4106 as PLL ICs. I have connected tantalum caps from Vcc line of VCO to gnd and spur rejection bacame better. also I have selected narrower loop filter and spur rejection bacame better too. But the lock time became longer. Is there any other way to reject spurs more? (The spur rejection is about 50dBc now).pls hlp.
    As Rich says, if you don't answer our questions we can't help you work out where the spurs are coming from, and without determining that it is hard to suggest a solution. There are lots of ways to reduce spurs, but without determining where the spurs are coming from it is hard to know what might work.

    What op amp are you using? Are the spurs at harmonics of the phase detector frequency? Is it a fractional-N or integer-N design?


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    •   Alt14th May 2009, 04:57

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    Re: PLL Problem [pls hlp me]

    Looks to me as if the PLL is not locked. Ensure the RF chain is not producing spuries.
    I have experence with the very old MC154152 and have had simular problems in the past. yell out if you cant solve it . Mark.

    Added after 5 minutes:

    As a start, go around with a scope and measure all the DC lines, if any of them have AC on them then you need to up you bypass caps. I have seen 7812 series regulators take off with 0.1uF caps on the input and outputs.


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    Re: PLL Problem [pls hlp me]

    Hello Fred, Hello Rich
    i have used AD820 from Analog Devices as the op amp of loop filter. It has been used in the ADIsimPLL simulation process. Also I have tested my design with both ADF4106 (integer-n) and ADF4156 (fractional); spurs were in the integer multiplications of ±50kHz. I want to test the proposed idea of fred, but if he sketch its schematic for me, it will be helpful.



    •   Alt17th May 2009, 11:22

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    Re: PLL Problem [pls hlp me]

    Hi Fred. Is there a web page that displays the circuit dia. you could point us to. If we can see the complete dia it would help. Mark.



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    Re: PLL Problem [pls hlp me]

    The idea is very simple, if the spurs are caused by leakage at the phase detector (from the chip itself, capacitors in the loop filter or input bias current of the op amp) then you can null out the effect simply by injecting the opposite current at the output of the charge pump.

    One way of doing this is to use a potentiometer connected between the charge pump supply (I'll assume 5V) and 0V. The wiper of the pot will vary from 0V to 5V. If you connect a large resistor (say 10M) from the wiper to the output of the charge pump then as you adjust the pot from 1V above the loop filter voltage to 1V below the current you inject varies from 100nA to -100nA. With care (and a 10-turn pot) you should be able to null out the spurs if they are caused by leakage.

    Another thing to check, is the output of the charge pump well away from saturating at either 0V or Vp? Note that the input bias current of the AD820 increases dramatically when the input voltage is above 4V.


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    Re: PLL Problem [pls hlp me]

    The idea is that if there is a leakage current somewhere (capacitor, op amp input), you can inject a compensating current into the op amp summing junction, and null out the net leakage current. IF this is your problem, your PFD is already providing a compensating current, and it is doing it the only way it knows how--by supplying spikes of current into the op amp summing junction at the rate of the reference frequency.

    If you set up a high value resistance, and hook it to an external power supply, you can inject (with a positive external voltage) or subtract (with a negative external voltage) a compensating current. If you get it just right, and the spurs go away in the spectrum, then this was your problem.

    You might have to adjust the resistor to a smaller value, if you are not getting enough adjustment range with the +/- power supply voltage.


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    Re: PLL Problem [pls hlp me]

    it looks like the PFD has some leakage.



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    Re: PLL Problem [pls hlp me]

    Hello friends
    I have used the idea advised by Fred and Rich; but the spurs are present yet and they aren't attenuated any more. pls advise another way.

    An exciting observation:
    When I design the loop filter for 300kHz bandwidth (by ADIsimPLL), the spurs are at ±n×50kHz steps from carrier. When LPF is designed for 100kHz bandwidth, the spurs are at ±6kHz from carrier and when LPF is designed for 25kHz bandwidth, the spurs are at ±3kHz from carrier!
    May the problem is caused by the loop filter topology? Is it better to use another topology as loop filter? hlp pls.



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    Re: PLL Problem [pls hlp me]

    Back to the list so far:
    1) too wide a loop bandwidth. (or another way of saying it, not enough lowpass filtering in the loop filter)? NO Because you can change the loop bandwidth and the spurs do not change in level.
    2) Marginally stable control loop, so that a little bit of reference spur energy is "ringing" and causing a lot of trouble? PROBABLY since when you change the loop bandwidths, the spur frequency changes.
    3) External noise, like from a noisy switching voltage regulator ? Still maybe, but since the spur frequency changes with the loop bandwidth change, it is unlikely. If an exernal switcher was causing the spikes, they would remain at the same frequency, and if an external linear regulator was oscillating, the oscillations woud not change frequency with loop filter bandwidth.
    4) Are you sure it is "phase locked". (if you vary the reference frequency 100 Hz, does the VCO frequency vary by 100 Hz * N exactly?) STILL do not konw.
    5) Is the spacing of the spurs mathematically related to the reference frequency used? If you vary R4 up and down, what happens to the spur level in dBc, and does the spacing of the spurs in frequency change? NO, apparently not.

    6) Are the op amp of components leaky? NO since you can not compensate for leakage.

    7) Is the op amp Oscillating (lack of bypass caps, etc)? Maybe

    It sounds most likely that 2) or 7) are the cause, although you should still check 4).

    First, make sure the op amp supply pins have 1 uF ceramic caps bypassed to ground right at the pins.

    Then try removing C3 completely and tell us what happens. If that helps but does not completely solve problem, try different values of R1 without changing C1 or C2 and tell us what happens.

    Is this some sort of actual spectrum analyzer test data you are measuing, or just a simulation?


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    Re: PLL Problem [pls hlp me]

    Hello Rich
    I'm working on an real PLL circuit!
    Another observation:
    It seems that spurs are created because I have used a single supply configuration for op-amp of loop filter. Is it true? How I can solve this problem? Designing the PLL again with complementary supplies?!! Oooooh! no! pls hlp!



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    Re: PLL Problem [pls hlp me]

    Hmmmm, single supply. Sometimes single supply op amps have some very weird input DC operating voltage requirements. This may be screwing up your charge pump. Which op amp part number? Also, is it a "rail to rail" op amp? If not, you might be operating in a non-linear condition for th op amp.

    Whenevery possible I like to use a dual supply op amp--less hassles.


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    Re: PLL Problem [pls hlp me]

    Hello Rich
    i'm using AD820 as op-amp of loop filter. Do you propose to change my design and use dual supply configuration? IS there any alternative solution?



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    Re: PLL Problem [pls hlp me]

    Quote Originally Posted by elec350
    Hello friends
    I have used the idea advised by Fred and Rich; but the spurs are present yet and they aren't attenuated any more. pls advise another way.

    An exciting observation:
    When I design the loop filter for 300kHz bandwidth (by ADIsimPLL), the spurs are at ±n×50kHz steps from carrier. When LPF is designed for 100kHz bandwidth, the spurs are at ±6kHz from carrier and when LPF is designed for 25kHz bandwidth, the spurs are at ±3kHz from carrier!
    May the problem is caused by the loop filter topology? Is it better to use another topology as loop filter? hlp pls.
    Let's start with basics, and if there is any doubt please give parameters associated with the design for the spectrum you posted initially:

    So to do with that first design:
    1. What is the output frequency, what is the phase detector frequency?
    2. is it integer-N or fractional-N, if fractional-N what is the modulus?
    3. is it locked - i.e. is the output frequency correct?
    4. what is the Vp supply to the chip and what are the supply rails to the op amp?
    5. what is the voltage on the + input to the op amp and the VCO voltage when locked?

    To do with your latest observations, are you changing any other parameters apart from the loop filter (e.g. are you changing the PD frequency or the modulus)? Are the measurements repeatable, when you reload the PLL do you see the same spectrum?


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    •   Alt26th May 2009, 07:28

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