brenox
Newbie level 5
rtl compiler set_attr
Hi, my name is Breno and I'm working with RTL Compiler.
The problem is that the new version of Cadence don't support the commands insert_scan and insert_boundary_scan.
To insert the boundary scan, it can still be done using the command build_top_shell of ET. But to insert the scan chains I have to use RC.
I'm trying to do this, reading the document Design for Test in Encouter RTL Compiler and following the steps. But I have a lot of questions about how to do it, because it has a lot of DFT violations and I can't fix them.
My difficulties are:
1. To use the command 'read_dft_abstract_model file' it needs a file that describes an architecture of the scan chains. Has it an standard file for this description?
2. In the command 'check_dft_rules' occurs many warnings due to the clock signals and async signals. I've tried to instantiate this signals, but I didn't have success.Other problem is that none of the registers pass trough the DFT Rules.
3. In the command 'set_attr lp_clock_gating_module' I can't set up a valid module.
4. I can't use the commands 'insert_dft shadow_logic' and 'insert_dft test_point'. Could it be because of the DFT violations?
So, the biggest problems are that I can't fix the violations. If anyone knows how to fix them, I can send the script and the reports. Could anyone help me?
Thank,
Breno
Hi, my name is Breno and I'm working with RTL Compiler.
The problem is that the new version of Cadence don't support the commands insert_scan and insert_boundary_scan.
To insert the boundary scan, it can still be done using the command build_top_shell of ET. But to insert the scan chains I have to use RC.
I'm trying to do this, reading the document Design for Test in Encouter RTL Compiler and following the steps. But I have a lot of questions about how to do it, because it has a lot of DFT violations and I can't fix them.
My difficulties are:
1. To use the command 'read_dft_abstract_model file' it needs a file that describes an architecture of the scan chains. Has it an standard file for this description?
2. In the command 'check_dft_rules' occurs many warnings due to the clock signals and async signals. I've tried to instantiate this signals, but I didn't have success.Other problem is that none of the registers pass trough the DFT Rules.
3. In the command 'set_attr lp_clock_gating_module' I can't set up a valid module.
4. I can't use the commands 'insert_dft shadow_logic' and 'insert_dft test_point'. Could it be because of the DFT violations?
So, the biggest problems are that I can't fix the violations. If anyone knows how to fix them, I can send the script and the reports. Could anyone help me?
Thank,
Breno