Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Timing violations in a design and how can i get rid of them?

Status
Not open for further replies.

badola

Member level 5
Joined
Jan 4, 2008
Messages
89
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,288
Location
bangalore
Activity points
1,786
timing violations

Hi,

can suggest me the kind of timing violations i can get in a design and how can i get rid of them? suggest some gud site or article from where i can get better idea. Your suggestions would be of great help for me. Thanking in advance.

Cheers
badola
 

timing violations

Types of violation: Setup, hold, recovery, removal, pulse width.

How to remove them?
setup: Redesign your logic, use more/better synthesis/layout optimisations, change techonology/libraries
hold: add buffers
 

Re: timing violations

hi,

pls refer attached docs.
it may help u.
thanks..

HAK..
 


Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top