felicia
Junior Member level 2
junior engineer + vlsi
Hi All,
We are looking for Junior ASIC/VLSI Engineer.
It is a permanent opportunity for a R&D center of a US company in Singapore.
Responsibilities:
• Design and verification of blocks
Requirements:
• BSEE + 1 year experience
• Proven experience with VLSI environment (Linux , simulators)
• Knowledge in verilog design and basic block flow
• Knowledge in C and basic test bench
• Experience with debug , RTL changes
• Familiarity with Synopsys tools - advantage
• Exceptional drive and motivational skills
If you are interested, please send your resume to felicia@uniconnect.com.sg
Thank you.
Hi All,
We are looking for Junior ASIC/VLSI Engineer.
It is a permanent opportunity for a R&D center of a US company in Singapore.
Responsibilities:
• Design and verification of blocks
Requirements:
• BSEE + 1 year experience
• Proven experience with VLSI environment (Linux , simulators)
• Knowledge in verilog design and basic block flow
• Knowledge in C and basic test bench
• Experience with debug , RTL changes
• Familiarity with Synopsys tools - advantage
• Exceptional drive and motivational skills
If you are interested, please send your resume to felicia@uniconnect.com.sg
Thank you.