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According to this figure: -2kV (negative zap) is applied at pin 1 with pin 2 at ground.
According to the figure (green reference line) there was a forward diode from pin 1 to pin 2 and some element for the reverse stress case (power clamp, local clamp or diode up + power clamp).
So this could be (example) pin 1 is a ground and pin 2 is an IO or a power supply. Then pin 1 is stressed with -2kV HBM which means that the power clamp or local clamp is triggered during this stress case. The stress has led to a short circuit failure (red line).
Let me know if you want to share further info to clarify in more detail.
ok , here are more detailed infos: it is a bipolar process, Pin 2 is connected to substrate , the voltage of pin 1 is always lower than pin 2 (i.e. substrate voltage is not the lowest voltage of the chip). Below is the main part of the circuit between pin 1 and pin 2. I hope you will give me more enlightenment about the failure.
Hi zhonghan,
So in reality there is not much to go on here. The image is from an old Zapmaster it looks like.
The green line is the pre-ESD-stressed curve trace showing that before ESD testing, pin 1 had a very strong forward biased diode (with Vt= ~0.7V) to a reference node for positive voltages, (if the reference node was pin 2, nothing in the schematic accounts for the strong diode...so I am wondering if there are some parasitic junctions related to the devices that are not explained by the schematic.)
...and a very resistive, possibly series diode path to the reference node for negative voltages.
What pin was used as reference for the curve trace...it may not have been pin 2.
The red curve is a curve trace post-ESD-stress, and shows a resistive fail (but you do not specify if your curve trace was between pin1 and 2 or pin 1 and some other ground...that matters too because it tells us to what node is pin 1 shorted...and its definitely shorted to something.
Other than that your pic doesn't tell much (other than pre and post stress curves...but nothing about what happened during the failure) and the schematic is not as useful without more understanding of the process.
I would suggest TLP to study the failure, FA if possible and also you need to take a hard look at both the parasitic junctions of the devices connected between pin 1 and 2 as well as who is shorted to Pin 1 as shown by the red line (in other words what pin was used as the reference for curve tracing pin 1...remember it may not have been pin 2).
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