Help me I am a new techie on FPGA

Hello Sir,

I am a new techie working on SPARTEN 3E

From net I came to know how to dump code < 4bits input and check output <=8bit

but I cant understand how to give inputs to a code having >4bits
and checking outputs > 8bit

can any one help me

Thank you
Ramesh

Hello Ramesh441,
In which language ur writing ur program VHDl r Verilog , What is the program ur write , will u post ur code here, then i can easily help u

Regards
Kanimozhi.M

I am using verilog

K, then Post Ur code, Do u know how to work in Xilinx,Which version of XIlinx UR using,will u post ur code here


Regards
Kanimozhi.M

I am working on xilix ISE webpack AND sPARTAN 3E KIT
I want to know how a 16 bit input is passed tested on spartan 3e kit i.e where will the 16 input 4 are switches and rest???

where will be the 16 output are seen only 8 are given for leds


presently iam not having any code
I hav an idea which requires these


Thank you
Ramesh

yes Ramesh, U can assign the inputin the program itself and using mux in ur code u take take the output in LEDS, If u have the code u can post it here, i will help u.

Regards
Kanimozhi.M

Hello sir this is my code

I want to give inputs
where in spartan 3e kit can i give inputs
and where can i find outputs
##################################################################


module rca(p, a, b);
output [15:0] p;
inout [7:0] a;
inout [7:0] b;

wire [7:0]c0,c1,c2,c3,c4,c5,c6,c7,s0,s1,s2,s3,s4,s5,s6,s7;
//stage0
singlecell st00(.s0(p[0]),.c0(c0[0]), .b(b[0]),.a(a[0]),.sin(1'b0), .cin(1'b0));
singlecell st01(.s0(s0[1]),.c0(c0[1]), .b(b[0]),.a(a[1]),.sin(1'b0), .cin(c0[0]));
singlecell st02(.s0(s0[2]),.c0(c0[2]), .b(b[0]),.a(a[2]),.sin(1'b0), .cin(c0[1]));
singlecell st03(.s0(s0[3]),.c0(c0[3]), .b(b[0]),.a(a[3]),.sin(1'b0), .cin(c0[2]));

singlecell st04(.s0(s0[4]),.c0(c0[4]), .b(b[0]),.a(a[4]),.sin(1'b0), .cin(c0[3]));
singlecell st05(.s0(s0[5]),.c0(c0[5]), .b(b[0]),.a(a[5]),.sin(1'b0), .cin(c0[4]));
singlecell st06(.s0(s0[6]),.c0(c0[6]), .b(b[0]),.a(a[6]),.sin(1'b0), .cin(c0[5]));
singlecell st07(.s0(s0[7]),.c0(c0[7]), .b(b[0]),.a(a[7]),.sin(1'b0), .cin(c0[6]));
//stage1
singlecell st10(.s0(p[1]),.c0(c1[0]), .b(b[1]),.a(a[0]),.sin(s0[1]), .cin(1'b0));
singlecell st11(.s0(s1[1]),.c0(c1[1]), .b(b[1]),.a(a[1]),.sin(s0[2]), .cin(c1[0]));
singlecell st12(.s0(s1[2]),.c0(c1[2]), .b(b[1]),.a(a[2]),.sin(s0[3]), .cin(c1[1]));
singlecell st13(.s0(s1[3]),.c0(c1[3]), .b(b[1]),.a(a[3]),.sin(s0[4]), .cin(c1[2]));

singlecell st14(.s0(s1[4]),.c0(c1[4]), .b(b[1]),.a(a[4]),.sin(s0[5]), .cin(c1[3]));
singlecell st15(.s0(s1[5]),.c0(c1[5]), .b(b[1]),.a(a[5]),.sin(s0[6]), .cin(c1[4]));
singlecell st16(.s0(s1[6]),.c0(c1[6]), .b(b[1]),.a(a[6]),.sin(s0[7]), .cin(c1[5]));
singlecell st17(.s0(s1[7]),.c0(c1[7]), .b(b[1]),.a(a[7]),.sin(c0[7]), .cin(c1[6]));
//stage2
singlecell st20(.s0(p[2]),.c0(c2[0]), .b(b[2]),.a(a[0]),.sin(s1[1]), .cin(1'b0));
singlecell st21(.s0(s2[1]),.c0(c2[1]), .b(b[2]),.a(a[1]),.sin(s1[2]), .cin(c2[0]));
singlecell st22(.s0(s2[2]),.c0(c2[2]), .b(b[2]),.a(a[2]),.sin(s1[3]), .cin(c2[1]));
singlecell st23(.s0(s2[3]),.c0(c2[3]), .b(b[2]),.a(a[3]),.sin(s1[4]), .cin(c2[2]));
singlecell st24(.s0(s2[4]),.c0(c2[4]), .b(b[2]),.a(a[4]),.sin(s1[5]), .cin(c2[3]));
singlecell st25(.s0(s2[5]),.c0(c2[5]), .b(b[2]),.a(a[5]),.sin(s1[6]), .cin(c2[4]));
singlecell st26(.s0(s2[6]),.c0(c2[6]), .b(b[2]),.a(a[6]),.sin(s1[7]), .cin(c2[5]));
singlecell st27(.s0(s2[7]),.c0(c2[7]), .b(b[2]),.a(a[7]),.sin(c1[7]), .cin(c2[6]));
//stage3
singlecell st30(.s0(p[3]),.c0(c3[0]), .b(b[3]),.a(a[0]),.sin(s2[1]), .cin(1'b0));
singlecell st31(.s0(s3[1]),.c0(c3[1]), .b(b[3]),.a(a[1]),.sin(s2[2]), .cin(c3[0]));
singlecell st32(.s0(s3[2]),.c0(c3[2]), .b(b[3]),.a(a[2]),.sin(s2[3]), .cin(c3[1]));
singlecell st33(.s0(s3[3]),.c0(c3[3]), .b(b[3]),.a(a[3]),.sin(s2[4]), .cin(c3[2]));
singlecell st34(.s0(s3[4]),.c0(c3[4]), .b(b[3]),.a(a[4]),.sin(s2[5]), .cin(c3[3]));
singlecell st35(.s0(s3[5]),.c0(c3[5]), .b(b[3]),.a(a[5]),.sin(s2[6]), .cin(c3[4]));
singlecell st36(.s0(s3[6]),.c0(c3[6]), .b(b[3]),.a(a[6]),.sin(s2[7]), .cin(c3[5]));
singlecell st37(.s0(s3[7]),.c0(c3[7]), .b(b[3]),.a(a[7]),.sin(c2[7]), .cin(c3[6]));

//stage4

singlecell st40(.s0(p[4]),.c0(c4[0]), .b(b[4]),.a(a[0]),.sin(s3[1]), .cin(1'b0));
singlecell st41(.s0(s4[1]),.c0(c4[1]), .b(b[4]),.a(a[1]),.sin(s3[2]), .cin(c4[0]));
singlecell st42(.s0(s4[2]),.c0(c4[2]), .b(b[4]),.a(a[2]),.sin(s3[3]), .cin(c4[1]));
singlecell st43(.s0(s4[3]),.c0(c4[3]), .b(b[4]),.a(a[3]),.sin(s3[4]), .cin(c4[2]));
singlecell st44(.s0(s4[4]),.c0(c4[4]), .b(b[4]),.a(a[4]),.sin(s3[5]), .cin(c4[3]));
singlecell st45(.s0(s4[5]),.c0(c4[5]), .b(b[4]),.a(a[5]),.sin(s3[6]), .cin(c4[4]));
singlecell st46(.s0(s4[6]),.c0(c4[6]), .b(b[4]),.a(a[6]),.sin(s3[7]), .cin(c4[5]));
singlecell st47(.s0(s4[7]),.c0(c4[7]), .b(b[4]),.a(a[7]),.sin(c3[7]), .cin(c4[6]));

//stage 5

singlecell st50(.s0(p[5]),.c0(c5[0]), .b(b[5]),.a(a[0]),.sin(s4[1]), .cin(1'b0));
singlecell st51(.s0(s5[1]),.c0(c5[1]), .b(b[5]),.a(a[1]),.sin(s4[2]), .cin(c5[0]));
singlecell st52(.s0(s5[2]),.c0(c5[2]), .b(b[5]),.a(a[2]),.sin(s4[3]), .cin(c5[1]));
singlecell st53(.s0(s5[3]),.c0(c5[3]), .b(b[5]),.a(a[3]),.sin(s4[4]), .cin(c5[2]));
singlecell st54(.s0(s5[4]),.c0(c5[4]), .b(b[5]),.a(a[4]),.sin(s4[5]), .cin(c5[3]));
singlecell st55(.s0(s5[5]),.c0(c5[5]), .b(b[5]),.a(a[5]),.sin(s4[6]), .cin(c5[4]));
singlecell st56(.s0(s5[6]),.c0(c5[6]), .b(b[5]),.a(a[6]),.sin(s4[7]), .cin(c5[5]));
singlecell st57(.s0(s5[7]),.c0(c5[7]), .b(b[5]),.a(a[7]),.sin(c4[7]), .cin(c5[6]));

//stage 6

singlecell st60(.s0(p[6]),.c0(c6[0]), .b(b[6]),.a(a[0]),.sin(s5[1]), .cin(1'b0));
singlecell st61(.s0(s6[1]),.c0(c6[1]), .b(b[6]),.a(a[1]),.sin(s5[2]), .cin(c6[0]));
singlecell st62(.s0(s6[2]),.c0(c6[2]), .b(b[6]),.a(a[2]),.sin(s5[3]), .cin(c6[1]));
singlecell st63(.s0(s6[3]),.c0(c6[3]), .b(b[6]),.a(a[3]),.sin(s5[4]), .cin(c6[2]));
singlecell st64(.s0(s6[4]),.c0(c6[4]), .b(b[6]),.a(a[4]),.sin(s5[5]), .cin(c6[3]));
singlecell st65(.s0(s6[5]),.c0(c6[5]), .b(b[6]),.a(a[5]),.sin(s5[6]), .cin(c6[4]));
singlecell st66(.s0(s6[6]),.c0(c6[6]), .b(b[6]),.a(a[6]),.sin(s5[7]), .cin(c6[5]));
singlecell st67(.s0(s6[7]),.c0(c6[7]), .b(b[6]),.a(a[7]),.sin(c5[7]), .cin(c6[6]));

//stage 7

singlecell st70(.s0(p[7]),.c0(c7[0]), .b(b[7]),.a(a[0]),.sin(s6[1]), .cin(1'b0));
singlecell st71(.s0(p[8]),.c0(c7[1]), .b(b[7]),.a(a[1]),.sin(s6[2]), .cin(c7[0]));
singlecell st72(.s0(p[9]),.c0(c7[2]), .b(b[7]),.a(a[2]),.sin(s6[3]), .cin(c7[1]));
singlecell st73(.s0(p[10]),.c0(c7[3]), .b(b[7]),.a(a[3]),.sin(s6[4]), .cin(c7[2]));
singlecell st74(.s0(p[11]),.c0(c7[4]), .b(b[7]),.a(a[4]),.sin(s6[5]), .cin(c7[3]));
singlecell st75(.s0(p[12]),.c0(c7[5]), .b(b[7]),.a(a[5]),.sin(s6[6]), .cin(c7[4]));
singlecell st76(.s0(p[13]),.c0(c7[6]), .b(b[7]),.a(a[6]),.sin(s6[7]), .cin(c7[5]));
singlecell st77(.s0(p[14]),.c0(p[15]), .b(b[7]),.a(a[7]),.sin(c6[7]), .cin(c7[6]));
//assign p[15:0]={c7[7],s7[7:0],s6[0],s5[0],s4[0],s3[0],s2[0],s1[0],s0[0]};
endmodule
module singlecell(s0,c0, b,a,sin, cin);
output s0;
inout a;
output c0;
inout b;
input sin;
// input a;
// input b;
input cin;
wire temp;
and a1(temp,a,b);
add_32 b1(
.s(s0),.c(c0),.a(sin),.b(temp),.cin(cin));


endmodule
module add_32(s, c, a, b, cin);
output s;
output c;
input a;
input b;
input cin;
wire x,y,z;
xor (s,a,b,cin);
and a1(x,a,b);
and a2(y,b,cin);
and a3(z,cin,a);
or (c,x,y,z);

endmodule
###########################################################################

Thank you
Ramesh

Hello Ramesh,

Your query is not so clear. But one thing i can suggest you is, be clear on the problem. Then start working on it step by step.

You have
1. xilix ISE webpack
2. SPARTAN 3E KIT
3. You have code (16 INPUTS and 16 OUTPUTS).

First understand the flow how to configure the code into FPGA board.

1. Develop UCF (user constraint) file.
2. In the UCF file mention which input is connected to which pin of FPGA.
3. And also mention which OUTPUT is connected to the LED in the board.
4. LED LOCCATION information will be given in the FPGA board reference manual.

So, my suggestion is to first develop the UCF .

Regards,
Sunil Budumuru

Hello Sir


You are correct

I synthesized my code
now I want to dump it in SPARTAN 3E kit

I could do it but while assigning input pins there are of 16 inputs and on boardd we are having only 4 switches


how could I assign rest of the pins

While checking output there is only 8 led on board how could we check the outputs (16)


Thank you
Ramesh

just leave the rest of the pins for the inputs

and

and just use 2 input OR gate and make ultimate 8 outputs (or)

Just use only 8 outputs and leave the rest. No problem....

Thank you for your reply sir,


Sir can you please say me totally how many inputs and how many outputs will be there in a spartan 3e and where are they present
and how to connect them

Actually I know very little basic s of the kit.

Thankyou
Ramesh

you can download the spartan datasheet from Xilinx. You can find all the required info there

I read it but its given about the switches and all stuff

Sir, if I want to give 8 inputs at a time to the spartan 3e kit how could I

see the IO bufferes in the spartan and verify the pin locations of that IO buffers.

Now in the UCF file u mention which input or Output pin is conected to the corresponsing IOs of spartan.

In the ucf use LOC .... kind of stuff. I did this long back.

Thank you so much for your Reply

I am I tring in that way
I hope I reached it

Thank you,
Ramesh