[SOLVED] Actel's SYSMGMT-DEV-KIT & debug problem with SoftConsole

m1afs-embedded-kit.zip

Hi All,

Right now I am working on (Actel’s) M1-SYSMGMT-DEV-KIT and not able to debug the code using SoftConsole.

I made one reference design with minimum components in Libero8.5 and have attached required information to debug this problem.

You can quckly made one new project in Libero and device selection information you will get from jpeg files in attachment.

Help will be appreciate.

Note:
1. If you are not able to open SG_TOP_DataSheet.xml file from attachment then please open it in WordPad and replace line2 with below line in that make correction indication with red color font and then open it in explorer.
<?xml-stylesheet type="text/xsl" href="file:///Folder Containing Libero Setup\LIBERO~1.5\Designer/data/datasheet/datasheet.xsl"?>

cortex m1 hello world

Hi!

I have exactly the same board and debugging is not working properly/at all in SoftConsole (v.2.2).

I have been trying to get these tutorials (ARM Cortex-M1 Embedded Processor Software Development Tutorial, ARM Cortex-M1 Embedded Processor Hardware Development Tutorial) to work from Actels page

http://www.actel.com/products/hardware/devkits_boards/fusion_embedded.aspx

My goal is simply to send text from uart to pc (HyperTerminal), but it just doesn´t work... how hard can it be?!

These tutorials should work straight, the only thing I really need to change were the I/O assignments in Libero to match my board. Also I need to match the linker script that i´m using to match the RAM and Flash sizes, starting addresses to the board.

With CoreABC everything worked fine. But now with Cortex M1 it isn´t so easy. I am "glad" that there´s somebody else than just me who have problems

What error is it giving for you? I had problems with JTAG chain, SoftConsole gave me an error "Remote Communication Error: No Error", solution was to add a jumper from JP16 pin 1 to JP17 pin 1, that will make the M1AFS1500-FG484 the only part in the chain.
Now debugging starts, it writes the code to flash, but when I run the code it looks like it´s running, but it doesn´t print anything to HyperTerminal and it gives me warning "<symbol is not available> 0x000000000".
I really don´t know anymore where´s the problem...

.pdb actel

HI,

If you want to debug the code on this kit you can made it possible by using internal CoreAhbSram or CoreAhbNvm at slot0 of your AHBlite in Libero smart design project.

You are getting symbol not available means there is some thing wrong in your Sram or Flash connections.

then try to debug code from internal Sram of Flash, if you are not able to short out this problem then.

Hth

Added after 54 minutes:


why you are taking reference of M1AFS Embedded Kit it have no use I think because in this kit there is Asynchronous Sram while on M1-SYSMGMT-DEV-KIT there is SSRAM so configuration setting of CoreMemCtrl will be cange you can take those design for reference of SmartGen.

I know as reference design for this kit was prepared by me only.

softconsole cortex-m1

Hi!

Thanks for your answer! They recommended from Actel to use this design. You are right that it needs changed a little bit. I have been trying to use internal Flash for debugging, but it´s not working right.

CoreMemCtrl is actually for an option if I use it later. If i am understanding right.. MEMREADN and MEMWRITEN should be connected to shared SSRAM/FLASH WRITEN/READN lines (pins A10, A5)? So CoreMemCtrl lines FlashOEN, FlashWEN, SRAMOEN and SRAMWEN can be marked unused?

In that reference design there is Flash Memory System: Data Storage Client in the project, but it is not connected anywhere in the design. I don´t fully understand the meaning of this, is the .hex file meant to put in there?

softconsole　hex　

Hi,

In M1-AFS1500-Embedded-Kit there is not extenal Flash at all. So Flash connections from CoreMemCtrl is un used and instead external flash internal non volatile memory is used and for that in SmartGen CoreAhbNvm is used and Data Storage client is used to initialize Internal Flash (Internal nonvolatile memory) with content given by hex file.

I am able to debug from intenal flash for M1-AFS1500-Embedded-Kit but same way for M1-SYS-MGMT-DEV-KIT not able to debug from intenal flash.



in which company r you working?

HTh
--
Shitansh Vaghela

debug chain actel

Hi,

Ah... thanks for clearing that up. I need to work with that problem..

I am actually from Finland and i am working in Kajaani University of Applied Sciences.

**broken link removed**

I assume that you are from India?

example m1afs

hi,

If you want then you can call me. We can work together for this problem.

my id is

shitansh_vaghela@yahoo.co.in

09898622277

Added after 3 hours 4 minutes:

Hi,

Just try this code attachted. program your afs with attached Nvm_Debug.pdb file and uzip Nvm_InternalSram_Debug.zip and import this project in SoftConsole_V_2.2.

If at first try it doesnt debug then terminate debugger and then relaunch it.

Let me know your experience. Make sure that AFS is in tool chain.

Note: This is for debugg via FlashPro.

Hth
--
Shitansh Vaghela

reference design for m1afs

Hello,

Thanks for the code! It worked fine, without any errors and printed "hello world".


EDIT:

Btw.. my email is:

jarno.kauppinen(at)kajak.fi

actel softconsole debug problem

Hi jarno

Do you able to debug your Libero project with Softconsole2.2 for SYS-MGMT-DEV-KIT, using CoreMemCtrl at slot0 of AhbLite? If yes then please send me your Libero Project.

Thanks

pdb actel

I have been trying, but it doesn´t work from CoreMemCtrl. But I will send it if I manage to get it work.

Added after 1 hours 56 minutes:

Finally I got my UART example working. Thank you very much Shitansh for the help! But I don´t still know how to get CoreMemCtrl to work.

I attached Libero design and SoftConsole project here. I hope that these files help beginners for the start because Actel´s examples have been limited for this board.

tutorial actel soft console cortex m1

Hi,

Using External SSRAM try this one, attached and let me know your experience.
For this you have to first program both FPGA (AFS and A3P) after that again keep AFS in tool chain.

Hth
--
Shitansh Vaghela

coreahbnvm data storage

Hi!

Looks like it´s working well. Is it possible to see what changes have you done to Libero design? I noticed that you have done some changes to linker script.
And what is the purpose of programming A3P?

Thanks,
--
Jarno Kauppinen

Re: Actel's SYSMGMT-DEV-KIT & debug problem with SoftCon

Hi,

Sure my friend i will send you the design. But it will be okey if i will send you by saturday or sunday as i will be on leave.

Let me give answer of your questions.

1. Our main problem was, we both not able to debug through extrnal SSRAM for this kit and Design point of view I was feeling that every thing is fine, then also The symptoms sound like we not able to access the ram at address 0. As shown in Schematic of Board that SSRAM FT pin is pulled up means we have to configure CoreMemCtrl for PipeLine. This is not working for both of us. Then I tried this way, FT pin of SSRAM is connected with A3P FPGA so i have assign this pin to Logic0 an it will work as pulled register is already present for this pin. So after doing this I configured CoreMemCtrl as Flow-Through mode with Synchronous Option.

The only line I have written for A3P is

module TOP
(
output SSRAM_FT // 0 FOR flowthrough, 1=Pipeline
);

assign SSRAM_FT = 1'b0;

endmodule



I think this explains you much any way i will try to send design up to noon.

Let me know if you want more expalination.

Hth

Hi Shitansh!

Thank you for the answer. That explains me a lot. A clever solution I must say. I will try to do that for my own project as well.

Re: Actel's SYSMGMT-DEV-KIT & debug problem with SoftCon

Hi,

Find Libero Design from ...

**broken link removed**
Note: Design will be deleted after 15 days.

Let me know your suggetion.

Hth
--
Shitansh Vaghela

Added after 32 minutes:

Sorry,

I have did one mistake in Configuration of COreMemCtrl that please correct it.

Any way for debug it is not going to affect but it may for stand alone application like boot from flash.

Hi,

Thanks! Looks like I had done everything right in my Libero design except that SSRAM_PWRDWN and FlashRPN pins doesn´t exist. So I have to manually "make" them.

Re: Actel's SYSMGMT-DEV-KIT & debug problem with SoftCon

Does not exist means I am not getting?

any way you have to connect SSRAM_PWRDWN to Logic0 else it will in sleep mode. you can see that in Datasheet of SSRAM.

Any way,

Really have a good experience to work with you.

Thanks
--
Shitansh Vaghela

I mean that outputs from CoreMemCtrl doesn´t include SSRAM_PWRDWN and FlashRPN pins. I had not realized that before now.

So I must create them in Libero and like you said, connect SSRAM_PWRDWN to Logic0 and FlashRPN to sys_reset.

It´s really nice to work with you too.

Re: Actel's SYSMGMT-DEV-KIT & debug problem with SoftCon

Hi

Can see someone working with Actel development kits....
I am new to this field and need some support from you guys.

I am using M1AGL-DEV-KIT-SCS.

First of all new to this, on top of that Softconsole is giving me lot of problems...

I took the example code from Actel and program it to the development board.

Now I am able to do in debug mode(debug option is getting highlighted)....but unable to do in release mode(run option is getting highlighted).

Should I make any settings in release mode. But as per my knowledge and as per datasheet nothing else is to be done.

Thanks in advance......

Re: Actel's SYSMGMT-DEV-KIT & debug problem with SoftCon

Hi,

I have some questions to solve your problem.

1. which version of Softconsole are you using?
2. Which version of LiberoIDE?
3. Have you read some documets related working with CortexM1?
4. For Release mode have you set Flash(InternalNVM or/ External Flash) at 0x00 address and initialize that with hex file?
5. which version of CoreMemCtrl and CoreAhBLite are you using?

I need answer of all these questions to help you more without that it is quite difficult to understand which problem you are facing.

--
Shitansh Vaghela