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DC compiler error in the analyze log file

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DC compiler error

Dear all

I have some very basic error using design compiler. In the top level VHDL code library is defined. some thing like this
library ieee;

use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

library XXX;
use xxx.xxx.all;

I am trying to synthesis the Top level and using the following command include the library

define_design_lib "xxx"" -path ~/xxx

I have this error in the analyze log file.

[Error] xxx is not a primary unit of library xxx

any help is greatlt appreciated

best regard

Sig
 

Re: DC compiler error

hi,
This is the problem with work libraries. check the use-clause in your RTL. The libraries included using USE clause in a design should be analyzed before analyzing the design.

make sure parameters file and utilities files are analyzed in order.
 

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