kuohsi
Member level 3
CIC decimator circuit
Hi ,all
I am designing a CIC decimator filter for sigma-delta ADC.
Can I assume the decimation rate R = 1024 ?
R = 1024 is a large number. Does it have a large circuit area?
How can I reduce the CIC filter area?
Thank you!
Hi ,all
I am designing a CIC decimator filter for sigma-delta ADC.
Can I assume the decimation rate R = 1024 ?
R = 1024 is a large number. Does it have a large circuit area?
How can I reduce the CIC filter area?
Thank you!