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CIC decimator circuit- How can I reduce the CIC filter area?

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kuohsi

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CIC decimator circuit

Hi ,all
I am designing a CIC decimator filter for sigma-delta ADC.
Can I assume the decimation rate R = 1024 ?
R = 1024 is a large number. Does it have a large circuit area?
How can I reduce the CIC filter area?
Thank you!
 

CIC decimator circuit

Plain CIC decimation is a technique from older days when the effort for multipliers that are needed for more sophisticated FIR filter decimators should be avoided. They are still useful. The number of bits needed in individual decimator stages, depending on R and other parameters can be found in literature.
 

CIC decimator circuit

You need to ask yourself a couple of questions first:
1. What is my decimation factor? Which you've stated as 1024.
2. You are looking at a CIC filter, so how far down does your first side lobe need to be? This will set the number of stages of the CIC filter.
3. Now you know you're number of stages, is your bandwidth small enough compared to your sample clock frequency, such that your wanted signal isn't being distorted by multiple stages?
4. You can also determine the number of registers and adders, plus the size of each register and adder for your determined number of stages, such that you can determine an area estimate. You can also parallel up some of the Comb and/or integrators to reduce size, but at the cost of increasing clock frequency thus power consumption.
 

Re: CIC decimator circuit

RBB said:
You need to ask yourself a couple of questions first:
1. What is my decimation factor? Which you've stated as 1024.
2. You are looking at a CIC filter, so how far down does your first side lobe need to be? This will set the number of stages of the CIC filter.
3. Now you know you're number of stages, is your bandwidth small enough compared to your sample clock frequency, such that your wanted signal isn't being distorted by multiple stages?
4. You can also determine the number of registers and adders, plus the size of each register and adder for your determined number of stages, such that you can determine an area estimate. You can also parallel up some of the Comb and/or integrators to reduce size, but at the cost of increasing clock frequency thus power consumption.

Thanks for your reply!
And then I will design a CIC decimator that 1-bit input and 16-bit output.
How can I calculate the SNR at the 16-bit output ?
How can I bulit and setting a CIC SIMULINK model?

Thank you very much!!
 

Re: CIC decimator circuit

How can I calculate the SNR at the 16-bit output ?
The question has to be answered by SD theory rather than CIC decimator properties.
 

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