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clock tree simulation - Astro or IC compiler ?

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Jeffrey1905

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clock tree simulation

I have question about how to simulation a clock tree using HSPICE or Nanosim for power and noise information on clock tree.

The procedure I am thinking is to extract clock tree from the design and then simulate. How can I extract clock tree? Can I use Astro or IC compiler to do that?

I would appreciate any suggestions. Thanks in advance.
 

Re: clock tree simulation

you want to analysis which aspect?
 
Re: clock tree simulation

I want to analyse the peak current and power consumption on the clock tree.

Hope this answers your question : )
 

clock tree simulation

Do you really need to do a transistor level sim for power analysis? I would have thought you could just extract a post-route Verilog netlist from Astro and simulate that capturing a SAIF/TCF file, which you can then use for power analysis in DC.

Depends how accurate you want the result to be, I guess. If you do want to do a very accurate spice sim, I guess you will need an extraction tool such as STAR-RCXT to create the netlist to simulate.
 
Re: clock tree simulation

Thanks for your reply. It is helpful. The DC Compiler can give a power analysis. But I want a more accurate one so as you said I might need Star-RCXT to create the netlist. I will keep trying and let you know. Please advise if any more suggestions. Thanks,
 
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