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Xilinx ISE 10.1 Mapping Phase problem

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FINALFANTASYFAN

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map problem in ise 10.1

Hi, everybody!

I'm doing a project which uses some Xilinx IP cores ( Division, Arctan,...). And I do not use all optional pins/outputs from these IPs. After being synthesized, design have more than 800 Slices but when it comes to Mapping, it is reduced to about 60 slices with Mapping report of trimming all unconnected pins and their related logics.

I opened Goals and Strategies, unchecked Reduce Unconnected Pins in Mapping. There are, however, some reductions in Mapping phase. And as loading these configurations into board ( Spartan 3E), 1 design worked well but 1 goes wrong although they are simulated well in ModelSIM.

Now I'm not sure whether it is because of ISE or it's my fault. Because I did simulate carefully in ModelSIM and it passed all.

Did anyone experience this or meet this circumstance? I wonder whether it's only my trouble ?
 

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