Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why Zero is coming in this circuit

Status
Not open for further replies.
P

pgoyal

Newbie level 3
Joined
Jan 28, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,308
Hello

I have a very very basic que. While doing cascode amplifier I observed one thing

Output impedence of cascode is (NMOS M1 bottom, M2 cascode)

rout = ro1 + ro2 +gm2.ro1.ro2

if there is a cap between M1 & M2
Then zo1 = r01 || 1/sC1 = r01/(1+r01.sC1)

Zout = Zo1 + ro2 + gm2.Zo1.r02
=(r01+r02+gm2.r01.r02) + s.ro1.ro2.C1
------------------------------------------------
1+ s.r01.C1

≈ (1+sC1/gm2)
----------------
(1+s.ro1.C1)
it shows a zero but I am not getting intutive reason behind it.
1) Is there any 2 paths which I am missing
2) there is nothing like half signal

<---Zout
******|
***----
--||****M2
***----
******|--------
**---- *****|
*-||**M1** -------
**----***** ------- C1
****|*******|
****Gnd****Gnd
 

try to replace each of the MOS by resistor for a clearer view.

for intuitive understanding, at low frequency u get just Rs, at higher frequency one of the Rs is decreased by the capacitor (that is a pole), at higher frequency the capacitor completely shorts the lower resistor and the effective resistance is the upper one (that is a zero)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top