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    verilog one shot

    Hi,

    I don't know how to write verilog code to generate a single pulse?

    Anyone can help?

    •   Alt26th January 2004, 04:44

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    verilog pulse

    this code i had writen to act as a digital mono stable but it it VHDL coding, I hope it may help



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    one shot verilog

    I'm not sure what your asking.. but theres this..

    thing is a high going transition which creates a oneshot pulsy at the same time..


    reg thing_dly;

    wire pulsy;
    assign pulsy = thing & ~thing_dly;

    always @(posedge clk or posedge rst)
    if(rst)
    thing_dly <= 1'b0;
    else
    thing_dly <= thing;


    If your looking for a quick pulse (say to clear a reg/combinatorial) then your coding the problem incorrectly.. never use gate delays.. there is always ways around it.. just hard to figure out..

    jelydonut



    •   Alt30th January 2004, 21:39

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    verilog create pulse

    I think this is what you want....
    // Verilog code
    module test001(clk, pulse, clkout);

    input clk;
    input pulse;
    output clkout;

    reg cnt, temp;
    initial begin cnt = 0;
    temp = 0;
    end

    always @(posedge clk)
    if(pulse && !cnt) begin
    cnt <= ~cnt;
    temp <= 1;
    end
    else if(!pulse) begin
    cnt <= 0;
    end
    else
    temp <= 0;


    assign clkout = temp|clk;

    endmodule
    WooOOOOOOOood


    1 members found this post helpful.

    •   Alt1st February 2004, 06:36

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    verilog pulse

    I think that generating a signal pulse must require a trigger signal.

    best reagrds




    Quote Originally Posted by dd2001
    Hi,

    I don't know how to write verilog code to generate a single pulse?

    Anyone can help?



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    verilog generate pulse

    I think it's no way to create a pulse in degital ckt,
    (use a faster clock is not a pulse)
    I think you need a hard-macro
    (Delay cell, use spice to calculate the delay to meet your pulse width)
    then in verilog:
    wire pulse,pulsed,pulse_want;
    dly(.out(pulsed), .in(pulse));
    assign pulse_want = pulse& ~pulsed;


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    create a pulse in verilog

    Ust two filp-flop to implement it.


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    one pulse code in verilog

    Your problem is not very clear. If you are having a clock signal and an enable signal which when arrives you must give out exactly one pulse, then, you can use two flips flops clocked by the same clock.
    O/p of the first flip flop goes as input to the second and the output of the second goes as I/p clear to the first, take o/p from the o/p of the first flip flop, this will be a single cycle pulse.
    Your enable can be any cycle width. Nest pulse will be generated only when enable comes for the second time. Tell me if it is clear ???



    •   Alt21st June 2005, 13:21

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    verilog one-shot

    from following attached file, you can find many design practice include

    signle pulse generate.



    best regards




    Quote Originally Posted by dd2001
    Hi,

    I don't know how to write verilog code to generate a single pulse?

    Anyone can help?


    1 members found this post helpful.

  10. #10
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    pulse in verilog

    Thanks!!!! It works fine.


    Quote Originally Posted by jelydonut
    I'm not sure what your asking.. but theres this..

    thing is a high going transition which creates a oneshot pulsy at the same time..


    reg thing_dly;

    wire pulsy;
    assign pulsy = thing & ~thing_dly;

    always @(posedge clk or posedge rst)
    if(rst)
    thing_dly <= 1'b0;
    else
    thing_dly <= thing;


    If your looking for a quick pulse (say to clear a reg/combinatorial) then your coding the problem incorrectly.. never use gate delays.. there is always ways around it.. just hard to figure out..

    jelydonut
    :D:D



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