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Making an FIR filter in fixed point VHDL

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mr_byte31

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hi all
i am making an FIR filter for practicing VHDL
what i need is :
work with fixed point like addition and mul
i use FPGA advantage 7.2 and i have xilinx 10.1 also
any suggestions??
 

vhdl fixed point

Hello,

I have the same problem, Did you solve your problem ?
 

vhdl fixpoint

Suggestions concerning what??
 

noise cancellation +digital filters +vhdl code

cld u tell us wht exactly are u expecting??
ur questn is not clear....

haneet
 

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