Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

checki ng of verilog netlist before Place & Route

Status
Not open for further replies.
V

viswanadh_babu

Member level 2
Joined
Apr 1, 2008
Messages
47
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Activity points
1,575
Hai all,

What are the various checks that are to be perfomed on prelayout verilog netlist by physical design engineer , before implementing P& R .

Regards,
KVB
 

1) No inputs should be floated.
2) There should not any assign statements.
3) All floating input connected to tie cells.
4) Adding Spare cells ( It depends on methodology, some guys will put in the P&R)
5) proper naming rules for the netlist etc....

Thanks,
Chaitanya.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top