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Formality: problem with design including clock-gating

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Alvin80

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formality clock gating

Hi everybody,
I'm a newbie of Formality tool environment.
I applied my own clock-gating technique on a design and I would like to validate that the optimization doesn't corrupt the behaviour of the design.
Functional verification passed usign NCSIM.
Formal verification didn't pass usign Synopsys Formality.
It seems that the tool doesn't manage the comparison between design with and without clock-gating (I also tried Synopsys standard clock-gating ). I suppose that it is impossible. The differences are at the inputs of the FF, but the outputs are the same both in the reference design and in the implemented design.
I found the variable 'verification_clock_gate_hold_mode' and I set it using all the different values (any, low, high).
Where could the problem be? :cry:
 

clock gating formal verification

hello friend,

Back trace from that inputs of FFs in both the REF and IMPL designs. U will land at the exact location of the problem. Good luck.
 

clock gating + formality

I suppose that my low-power optimization of the design can change something in the circuit and so the waveform of some signals will be different w.r.t. the original design.
However, the changes don't have to affect the behaviour of the entire circuit and so the output of each single FF has to be the same before and after the optimization.

For example, this happens after a standard clock-gating optimization where the waveform of the clock changes but the behaviour of the output of FF doesn't change.
My optimization is a particular clock-gating technique.

I suppose that the tool can understand the design is changed but it works properly!
I find the variable 'verification_clock_gate_hold_mode'... could be useful to set it properly? Is it enough?

Thanks in advance
 

clock gating formality

You can try to desactivate the matching by signature analysis with the command :

set verification_analysis_match_compare_points FALSE

Nicolas
 

formality unmatched

I believe Formality, as any FV tool should, have a mode to place ICGs in transparent mode...if you are using ICGs.
 

clock gating cell formality

Alvin80 said:
I suppose that my low-power optimization of the design can change something in the circuit and so the waveform of some signals will be different w.r.t. the original design.
However, the changes don't have to affect the behaviour of the entire circuit and so the output of each single FF has to be the same before and after the optimization.

For example, this happens after a standard clock-gating optimization where the waveform of the clock changes but the behaviour of the output of FF doesn't change.
My optimization is a particular clock-gating technique.

I suppose that the tool can understand the design is changed but it works properly!
I find the variable 'verification_clock_gate_hold_mode'... could be useful to set it properly? Is it enough?

Thanks in advance
Click to expand...

Did you find a solution for your problem?
I'm having a similar situation as yours...I need to compare two RTLs, with and without clock gating...And I just don't know how to make the matching pass only when the unmatching elements are the clock gate latches...!
 

how to handle clock gates in formality

if you hace used scanable clock gating cell, did you tie TE (test enable) input to 0 while comparing RTL against netlist??


can you please paste your formality unmatched points? I am sure, for clock gating cell you are not getting 'un-equivalent' poins .. it will show it as 'un- reachable' or something like that .. if that is the case, you can ignore it safely ...

Good luck
 

how to handle clock gating in formality

Alvin80 said:
Hi everybody,
I'm a newbie of Formality tool environment.
I applied my own clock-gating technique on a design and I would like to validate that the optimization doesn't corrupt the behaviour of the design.
Functional verification passed usign NCSIM.
Formal verification didn't pass usign Synopsys Formality.
It seems that the tool doesn't manage the comparison between design with and without clock-gating (I also tried Synopsys standard clock-gating ). I suppose that it is impossible. The differences are at the inputs of the FF, but the outputs are the same both in the reference design and in the implemented design.
I found the variable 'verification_clock_gate_hold_mode' and I set it using all the different values (any, low, high).
Where could the problem be? :cry:
Click to expand...

Is the problem in having unmatched points, or failing points?!
As Jaydip said, I'll repeat => make sure you put values for extra ports added in the gated design...tie them to 1 or 0...
 

use this command in your formality script

set verification_clock_gate_hold_mode <high | low | any>
 

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