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For Gatelevel simulation with output of DesignCompiler

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themeis

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Dear engineer people

I 'd like to get your advice.
With Virsim, I wanted to simulate my gate-level netlist synthesized by DesignCompiler.

With the synthesized netlist and library file, I used virsim.
However, I couldn't simulate because the library file (~~~.lib) is Asic standard cell library; It is not a verilog-format library.

How can I convert the asic library file to verilog library?
Could anybody comment about that?
Thank you a lot.

P.S. Can I just simulate my netlist with asic standard library in Virsim?
 

I think these lib files are binary and you cant convert them.

I hope some senior members could throw some more light
 

Hi themis,
You cant do GLS with .libs. You need Verilog/VHDL behavioral models for the GLS (These Verilog/VHDL libraries will exactly mimic the behaviour of .LIB cells). I think the same Foundry vendor will supply the Verilog/VHDL library models for the GLS sims.

-Paul
 

Hi,
No sure about synopsys tool but conformal can write out verilog models after reading .Lib libraries.

Regards;
 

Its good atleast Cadence tool has the capability to write-out Verilog model from .LIB. Please publish the way to write-out Verilog model from the .LIBS.

-Paul
 

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