Using DSP for measuring carrier phase

I am not a DSP guy by any means. But I have a problem that might be best solved by a DSP chip. If I have an IF signal, say at 10 MHz unmodulated carrier, and I want to compute its phase to a resolution of 0.1 degree, how would I have to process it. In other words, what ADC clock rate, how many bits in the ADC, and how many samples of the 10 MHz signal would I have to take to get to that resolution.

I had someone tell me that I can use a digital downconverter (DDC) function to multiply my phase resolution by a factor of 100.

I need to take enough samples to compute the phase, and then very quickly jump to a new signal and do it all over again. I am wondering how long I need to dwell (how many ADC samples) on each signal to get the answer.

Perhaps other forum members can give a profound theoretical answer. I prefer to suggest a few parameters of a possible design.

- low-pass filtering of the input signal below 2*fc
- ADC sampling at 4*fc, 10-14 Bit
- vectorial I/Q signal processing

The minimal measurement time depends mainly on signal and ADC noise, it can be estimated using the above sketched signal processing model.

As an important condition not yet mentioned, what's the reference phase for the measurement? If it's a fixed 10 MHz reference signal, the resolution can be most likely improved by phase locking the ADC to the reference. The ADC clock jitter is a critical parameter. Recent ADC have e.g. 0.5 ps RMS jitter, it gonna be rather difficult to provide a clock of similar purity.

By vectorial I/Q signal processing, I assume you mean that the I/Q is generated AFTER the ADC?

The way we are doing it now is a non-DSP approach, with an RF I/Q mixer, with the I and the Q fed as video signals into two ADC's. We are tired of living with the DC offset and I/Q plane distortions of an RF I/Q mixer!

Yes I meant I/Q processing after ADC. Also a two channel ADC quadrature sampling would be a solution, but it's more interesting at higher input frequencies, that don't easily allow oversampling.

Analog quadrature mixing and slow baseband ADC processing would be the method to avoid high speed DSP hardware. It's the way used in traditional VNA instruments. As an obvious advantage, it's not limited by ADC or DSP speed. I think however, that for a rather low 10 MHz carrier frequency, direct digitizing means less effort and better performance.

biff44 said:

I am not a DSP guy by any means. But I have a problem that might be best solved by a DSP chip. If I have an IF signal, say at 10 MHz unmodulated carrier, and I want to compute its phase to a resolution of 0.1 degree, how would I have to process it. In other words, what ADC clock rate, how many bits in the ADC, and how many samples of the 10 MHz signal would I have to take to get to that resolution.

I had someone tell me that I can use a digital downconverter (DDC) function to multiply my phase resolution by a factor of 100.

I need to take enough samples to compute the phase, and then very quickly jump to a new signal and do it all over again. I am wondering how long I need to dwell (how many ADC samples) on each signal to get the answer.

Click to expand...

Answer about "how long" is given by Cramer-Rao low bound (CRLB)
For getting phase measure variance S under signal/noise conditions SNR
you should take more than N samples

S > 1/(2*N*SNR) radians squared

Look at
**broken link removed**
or search CRLB elsewhere