jbs87
Newbie level 6
coolrunner ii starter kit
Hi:
How do I drive multiple 7 segment displays on a coolrunner II starter kit. I have the verilog code for the decoder
module lcd(bcd,leds);
input [3:0] bcd;
output [1:7] leds;
reg [1:7] leds;
always@(bcd)
case(bcd) //
0:leds = 7'b1111110;
1:leds = 7'b0110000;
2:leds = 7'b1101101;
3:leds = 7'b1111001;
default:leds = 7'bx;
endcase
endmodule
And i know I have to edit the UCF file to output to the 7 seg display
#PACE: Start of PACE I/O Pin Assignments
NET "leds<1>" LOC = "p56" ;
NET "leds<2>" LOC = "p53" ;
NET "leds<3>" LOC = "p60" ;
NET "leds<4>" LOC = "p58" ;
NET "leds<5>" LOC = "p57" ;
NET "leds<6>" LOC = "p54" ;
NET "leds<7>" LOC = "p61" ;
How do i select which of the 4 seven segement displays to drive and specify whether it is on or off? Is what I have so far right? Also lets say I have two switches which i want to use as inputs. That would be a two bit number. How do i specify that in the UCF? I tried assigning the switch location to both bits but it does not allow that. I'm a total newb at this stuff and any help in Verilog would be appreciated.
Hi:
How do I drive multiple 7 segment displays on a coolrunner II starter kit. I have the verilog code for the decoder
module lcd(bcd,leds);
input [3:0] bcd;
output [1:7] leds;
reg [1:7] leds;
always@(bcd)
case(bcd) //
0:leds = 7'b1111110;
1:leds = 7'b0110000;
2:leds = 7'b1101101;
3:leds = 7'b1111001;
default:leds = 7'bx;
endcase
endmodule
And i know I have to edit the UCF file to output to the 7 seg display
#PACE: Start of PACE I/O Pin Assignments
NET "leds<1>" LOC = "p56" ;
NET "leds<2>" LOC = "p53" ;
NET "leds<3>" LOC = "p60" ;
NET "leds<4>" LOC = "p58" ;
NET "leds<5>" LOC = "p57" ;
NET "leds<6>" LOC = "p54" ;
NET "leds<7>" LOC = "p61" ;
How do i select which of the 4 seven segement displays to drive and specify whether it is on or off? Is what I have so far right? Also lets say I have two switches which i want to use as inputs. That would be a two bit number. How do i specify that in the UCF? I tried assigning the switch location to both bits but it does not allow that. I'm a total newb at this stuff and any help in Verilog would be appreciated.