pll veriloga simulation of pss,pnoise

site:www.edaboard.com pll veriloga

Hi ,

When I simulate pss,pnoise of pll(VCO ,PFD ,Divider are written with veriloga), some error comes:

Error found by spectre during periodic steady state analysis `pss'.
Distributed components and components with hidden state are not allowed
with this analysis -- analysis skipped.

CP

/home/pll/veriloga/CP/veriloga/veriloga.va, line 25:
Hidden state variable: state

Divider

/home/pll/veriloga/Divider/veriloga/veriloga.va, line
19: Hidden state variable: cnt
/home/pll/veriloga/Divider/veriloga/veriloga.va, line
21: Hidden state variable: cnt
/home/pll/veriloga/Divider/veriloga/veriloga.va, line
22: Hidden state variable: cnt
/home/pll/veriloga/Divider/veriloga/veriloga.va, line
23: Hidden state variable: cnt

Analysis `pss' terminated prematurely due to error.


So, it seems that some variable in veriloga cannot be simulated in PSS. Anyone can solve this problem?

pll veriloga simulation

I guess you have to define these variables somewhere, may be (additionally?) in the ADE setUp.

Re: pll veriloga simulation

erikl said:

I guess you have to define these variables somewhere, may be (additionally?) in the ADE setUp.

Click to expand...

Just set some value in the ADE setup???

pll veriloga simulation

I think so. Reasonable values, of course. Just try it!

i heard, you must disable SOAC from utilities but i havent tried.