yangbay81983
Newbie level 4
16bits rotate left
can I write verilog like this:
rotate_left:
//Need 16 2-to-1mux to finish 1-bit shift left
if (!Cnt[0])
in_stage2[15:0] = In[15:0];
else
in_stage2[15:0] = {In[14:0],In[15]};
//Need 16 2-to-1mux to finish 2-bit shift left
if (!Cnt[1])
in_stage3[15:0] = in_stage2[15:0];
else
in_stage3[15:0] = {in_stage2[13:0],in_stage2[15:14]};
//Need 16 2-to-1mux to finish 4-bit shift left
if (!Cnt[2])
in_stage4[15:0] = in_stage3[15:0];
else
in_stage4[15:0] = {in_stage3[11:0],in_stage3[15:12]};
//Need 16 2-to-1mux to finish 8-bit shift left
if (!Cnt[3])
Out[15:0] = in_stage4[15:0];
else
Out[15:0] = {in_stage4[7:0],in_stage4[15:8]};
A lot of errors when compiling. Thank you
can I write verilog like this:
rotate_left:
//Need 16 2-to-1mux to finish 1-bit shift left
if (!Cnt[0])
in_stage2[15:0] = In[15:0];
else
in_stage2[15:0] = {In[14:0],In[15]};
//Need 16 2-to-1mux to finish 2-bit shift left
if (!Cnt[1])
in_stage3[15:0] = in_stage2[15:0];
else
in_stage3[15:0] = {in_stage2[13:0],in_stage2[15:14]};
//Need 16 2-to-1mux to finish 4-bit shift left
if (!Cnt[2])
in_stage4[15:0] = in_stage3[15:0];
else
in_stage4[15:0] = {in_stage3[11:0],in_stage3[15:12]};
//Need 16 2-to-1mux to finish 8-bit shift left
if (!Cnt[3])
Out[15:0] = in_stage4[15:0];
else
Out[15:0] = {in_stage4[7:0],in_stage4[15:8]};
A lot of errors when compiling. Thank you