Deserializer & Serializer!! Help Needed!!

xilinx deserializer фвы

Hi guys,

Anyone can give me an idea of how to develop the building blocks in yellow? I'm using Virtex4 VLX100 FPGA chip.

Any help will be greatly appreciated!!

deserializer

jeremylbt,

The logic for the yellow blocks themselves will be very simple. For the demux you simply grab 16 16-bit words and then do a 256 bit write to the ram. For the mux, you read a single 256-bit and then do 16 16-bit writes out on the line.

The hard part is going to be getting your logic at the Virtex interface to run at the 625 MHz clock required to keep up with the line traffic. You can run the logic interfacing to the ram at 39 MHZ and keep up with the line so that shouldn't be a problem.

Are the clocks used for the 625 MS/s lines asynchronous to the your internal virtex clock?

Start with looking at how you're going to capture your data (async fifo?) and then try to get a feel for how you're going to hand the data off to your ram interface logic. You're going to want to drop the data rate down as fast as you can if you want to have any chance of meeting timing with the rest of your logic.

Radix

Hi Radix,

Thank you for your quick reply.

First of all, the clock used for the internal virtex is derived from the clock used to drive the line.

So for the demux part, I will need a FIFO to capture the data coming in at 625MHz and write the 256bit vector into the RAM at 39MHz. Is the FIFO about to run at 625Mhz?

For the mux part, how am I able to grab the 256bit vector from the RAM and output 16bit vectors at 625Mhz? Please advise

One last question, say the top level entity consists of the demux, RAM and mux, do i need to synthesize the top entity to 625Mhz. Is it possible for virtex 4 to run at such speeds?

Thank you very much..

This is like an exact copy of a design I did in 1999
I really doubt you can run a 32bits data @ 625MHz on virtex 4. Back then I managed to get 170MHz as my max frequency, but I had to split the path into 2x32bits @ 170/2 MHz.

I think you maybe able to tweak your design and run 2 different path and run each of them at half the frequency but even that is way too high for V4 and even for the laters V5 if can be tough to do.

Jeremyblt,

I haven't used an FPGA for processing data at the speeds you're shooting for and it is going to be challenging.

I would take a look at the virtex4 user guide and read the section "Advanced SelectIO Logic Resources". I'm not sure how many iserdes modules are available in the virtex4 parts, but if you had 16 of them you could use them in a 1:8 configuration and drop your line rate down to 78 Mbps (128-bit wide data). You would also need 16 more iserdes on the output side in a 8:1 configuration.

If you do have enough iserdes modules this approach will only work if your interface to the 625 Mbps data is differential. If it is single-ended I think you might be screwed because the SelectIO technology only works up to 600 Mbps in this case.

If you can actually process the data at the required speeds, the way that you read the data out of the RAM is going to be the reverse process of how you chose to store the data in memory. If you get to this point either post here or drop me a line and I can help.

Good luck,
Radix

I just finished a case of deserialize from 16bit_622MHz to 32bit_311M. You can refer to the attachment. The source code isn't inclued in file which is delivered by Xilinx FAE.

Hi Hellokid,

Since the output of ISERDES available in virtex 4 is only up to 10 (Master and slave mode), does it means i can only have max 1:10 deserialization factor?

Thank your Radix and farhada for your help as well!!

I think you have missunderstood me. In ur figure, all ur need to do is to transfer high speed 16bit data to low speed 256bit. It don't need FPGA's RocketIO to SERDES/DESERDES which is called 'hard SERDES'. The file I had attached a couple days ago is using technic called DPA(dynamic phase align) can transfer 16bit 622MHz to 32bit 311MHz or 64bit 155MHz, and so on. We call this as "soft serdes". It can be instanced at those normal SelectIO.

Hi Hellokid,

I understood what you meant and i'm using instantiated ISERDES/OSERDES from SelectIO resources. I'm not using RocketIO which is not available in virtex4 LX family chip anyway.

Each ISERDES can only output up to 10 bits of data if u use master n slave mode. What I wan to put across is the fact that i need 1:16 deserialization for my 16 bit data to deserialize to 256 bits. How can i achieve this based on the technique that you have attached?

I may not have understood the attachment fully. Please enlighten me. Thank you very much!!

The code is a sample of transfer from 16bit 622MHz to 32bit 311MHz.
You can do it in two steps.
first, deserdes from 16bit 622MHz to 64bit 155M with the code attached.
second, deserdes 64bit 155Mhz to 256bit 39Mhz with your own way (daul port ram or Flip-flop divider).

Hi HelloKid,

Thank you for your help. Appreciate it!