- 30th January 2009, 10:30 #1

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## transconductance parameter

Hello everyone

I need transconductance parameter Kn of the NMOS and Kp of the PMOS .

from website MOSIS, i download spice model parameter TSMC 0.18µ ,CR018 (CM018) (mixed-mode).

*****************************Spice Model*****************************

.MODEL NMOS NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9

+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3631313

+K1 = 0.5920712 K2 = 3.261973E-3 K3 = 1E-3

+K3B = 2.9061018 W0 = 1E-7 NLX = 1.840449E-7

+DVT0W = 0 DVT1W = 0 DVT2W = 0

+DVT0 = 1.4767146 DVT1 = 0.4177419 DVT2 = 8.829889E-3

+U0 = 255.1380803 UA = -1.597788E-9 UB = 2.53505E-18

+UC = 4.766568E-11 VSAT = 1.010331E5 A0 = 1.80776

+AGS = 0.3951935 B0 = 2.536033E-7 B1 = 5E-6

+KETA = -5.061981E-3 A1 = 5.396345E-4 A2 = 0.8936768

+RDSW = 111.58989 PRWG = 0.5 PRWB = -0.2

+WR = 1 WINT = 0 LINT = 1.840173E-8

+XL = 0 XW = -1E-8 DWG = -5.605289E-9

+DWB = 1.137609E-8 VOFF = -0.0871468 NFACTOR = 2.3018187

+CIT = 0 CDSC = 2.4E-4 CDSCD = 0

+CDSCB = 0 ETA0 = 3.127659E-3 ETAB = 9.485027E-6

+DSUB = 0.018202 PCLM = 0.7464953 PDIBLC1 = 0.2263045

+PDIBLC2 = 2.358517E-3 PDIBLCB = -0.1 DROUT = 0.8266278

+PSCBE1 = 4.915846E10 PSCBE2 = 2.831646E-9 PVAG = 0.010936

+DELTA = 0.01 RSH = 6.6 MOBMOD = 1

+PRT = 0 UTE = -1.5 KT1 = -0.11

+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9

+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4

+WL = 0 WLN = 1 WW = 0

+WWN = 1 WWL = 0 LL = 0

+LLN = 1 LW = 0 LWN = 1

+LWL = 0 CAPMOD = 2 XPART = 0.5

+CGDO = 8.4E-10 CGSO = 8.4E-10 CGBO = 1E-12

+CJ = 9.619152E-4 PB = 0.8 MJ = 0.3787773

+CJSW = 2.61908E-10 PBSW = 0.8 MJSW = 0.157929

+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.157929

+CF = 0 PVTH0 = -6.300783E-5 PRDSW = -2.1729835

+PK2 = 9.978988E-4 WKETA = 8.888859E-5 LKETA = -6.31897E-3

+PU0 = 4.3665601 PUA = 9.428511E-14 PUB = 0

+PVSAT = 1.356405E3 PETA0 = 1.003159E-4 PKETA = -1.583628E-3 )

*

.MODEL PMOS PMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9

+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3706453

+K1 = 0.5740728 K2 = 0.0277093 K3 = 0

+K3B = 7.9502396 W0 = 1E-6 NLX = 1.195464E-7

+DVT0W = 0 DVT1W = 0 DVT2W = 0

+DVT0 = 0.6525814 DVT1 = 0.2558611 DVT2 = 0.1

+U0 = 103.6542095 UA = 1.044279E-9 UB = 1E-21

+UC = -1E-10 VSAT = 1.528072E5 A0 = 1.6482476

************************************************** *****************

Kn =µ0 * Cox

we haven't the value of Cox

Thank you in advance for your help

Fasto

- 30th January 2009, 13:47 #2

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## kn kp

Originally Posted by**fasto2008**

Cox = Epsilon(SiO2) / TOX

Epsilon(SiO2) = Epsilon(0) * Epsilon(SiO2,rel) = 8.854e-12 F/m * 3.9

--> Cox = 8.422e-3 As/Vmjavascript:emoticon('%C2%B2') javascript:emoticon('%E2%89%88') 8.4 fF/(µm)javascript:emoticon('%C2%B2')

HTH, erikl

- 30th January 2009, 13:47

- 30th January 2009, 14:36 #3

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## process transconductance parameter

Check this site for detailed explaination of the BSIM3 model. Whenever you start with a new process its a good idea to do characterisation of the the MOSFETs in simulation.

The parameter values you see in the model are not always the actual stuff. They are curve fitting parameters that were extracted from silicon characterisation when the process is first done.

- 30th January 2009, 15:07 #4

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## transconductance parameters

Originally Posted by**kishore2k4**

as for u0, it is normally curve fitting parameter..... for hand calculation u can use default value from BSIM3 document......

for characterisation, it is good to use large W and large L, ie 10/10um as it has very small effect on the small length and narrow width effect

- 31st January 2009, 03:58 #5

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## process transconductance

Is a Epsilon(SiO2) constant in common use of any porcess (TSMC and UMC) ?

- 31st January 2009, 03:58

- 31st January 2009, 10:56 #6

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## tsmc 0.18 model parameter

Hello everyone

Realy with your help

Thank you very much,i found Kn an Kp in Spice Model

******************Model***********************

MOSIS PARAMETRIC TEST RESULTS

RUN: T49P (MM_NON-EPI) VENDOR: TSMC

TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns

INTRODUCTION: This report contains the lot average results obtained by MOSIS

from measurements of MOSIS test structures on each wafer of

this fabrication lot. SPICE parameters obtained from similar

measurements on a selected wafer are also attached.

COMMENTS: DSCN6M018_TSMC

TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS

MINIMUM 0.27/0.18

Vth 0.50 -0.51 volts

SHORT 20.0/0.18

Idss 591 -293 uA/um

Vth 0.52 -0.51 volts

Vpt 4.6 -5.4 volts

WIDE 20.0/0.18

Ids0 22.8 -20.3 pA/um

LARGE 50/50

Vth 0.43 -0.41 volts

Vjbkd 3.1 -4.1 volts

Ijlk <50.0 <50.0 pA

K' (Uo*Cox/2) 170.7 -36.1 uA/V^2

Low-field Mobility 405.36 85.73 cm^2/V*s

************************************************** **********

Thank you for everyone

FASTO

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- 31st January 2009, 10:56

- 31st January 2009, 13:59 #7

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## kn nmos

Originally Posted by**neter**__3.9__.

Added after 41 minutes:

Originally Posted by**fasto2008**

Cox = 8.422e-3 F/m^2 = 0.8422 µAs/V(cm)^2

Cox/2 = 0.4211 µAs/V(cm)^2

... you get exactly these values

Kn = 405.36 cm^2/Vs * 0.4211 µAs/V(cm)^2 = 170.7 uA/V^2

Kp = 85.73 cm^2/Vs * 0.4211 µAs/V(cm)^2 = 36.1 uA/V^2

Cheers, erikl

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- 1st March 2012, 04:32 #8

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## Re: transconductance parameter

Hi,

Can you share the whole library model for nmos and pmos specified below. We see that NMOS is full, but pmos is not described fully here. Could you please share it for us to do some experiments and also the Kp and Kn values you have computed for this library.

Thanks a lot.

Regards,

abdj

- 1st March 2012, 11:52 #9

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## Re: transconductance parameter

It's published and available ...

See here.

- 2nd March 2012, 03:06 #10

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## Re: transconductance parameter

Hi,

Thanks a lot.

So for this model, we should take Kn = 171.2u and Kp = 36.1u right?

Actually Kn = µnCox, where Cox we can calculate as εsi/Tox. Tox is available in the library. But how can we take the µn value. There is a U0 value in the library. Is this what we have to take for calculation? But U0=270.9714861 for NMOS and U0=103.9954725 for PMOS. With this we need to calculate?

When ever you have used this library, have you designed circuits with Kn = 171.2u and Kp = 36.1u ? Because for design Kn and Kp values are very important rt.

Also here K' is specified in library as µnCOx/2. Actually when we design, we use Kn as µnCox only. So do we need to multiply the given values Kn = 171.2u and Kp = 36.1u by 2?

Thanks,

abdj

- 2nd March 2012, 14:02 #11

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## Re: transconductance parameter

Depends on the run lot. For the ...

Code:RUN: T49P (MM_NON-EPI) VENDOR: TSMC TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns

Code:K' (Uo*Cox/2) 170.7 -36.1 uA/V^2

No. With the extracted**U0**values from SPICE you get Kn=228 µA/V^{2}resp. Kp=87.6 µA/V^{2}.

I never used this lib, sorry. But if you got these values from a lib (or from TSMC lot run test results), you better use these values; they already represent the K'=K/2 values for your calculations.

Depends. As mentioned above, these K' values are correct for your calculations (those which need K'=µ*Cox/2).

For those calculations which need K=µ*Cox you have to multiply by 2 of course.

- 3rd March 2012, 07:07 #12

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## Re: transconductance parameter

Thanks erikl,

We have few more doubts. We are not at all familiar with mos libraries and hence facing a lot of trouble in simulating circuits. Circuit details given below. Could you please share a mos hspice model library you are using which is working correctly for us to try some circuits. We would like to have level49 library for which we know accurate Kn, Kp, Vth, ΔVth values. Please help as we are finding it very very very difficult to solve issues as we don't understand library values well. Sorry for trouble. Circuit details given below

Actually we were trying to design a simple 2-stage opamp as shown in figure below.

2stage_opamp.PNG

The library we are using is :

-----------------------------------------------------------------------------------------------------------------

MOSIS PARAMETRIC TEST RESULTS

RUN: T49P (MM_NON-EPI_THK-MTL) VENDOR: TSMC

TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns

INTRODUCTION: This report contains the lot average results obtained by MOSIS

from measurements of MOSIS test structures on each wafer of

this fabrication lot. SPICE parameters obtained from similar

measurements on a selected wafer are also attached.

COMMENTS: DSCN6M018_TSMC

TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS

MINIMUM 0.27/0.18

Vth 0.50 -0.50 volts

SHORT 20.0/0.18

Idss 602 -306 uA/um

Vth 0.51 -0.50 volts

Vpt 4.7 -5.4 volts

WIDE 20.0/0.18

Ids0 32.5 -29.6 pA/um

LARGE 50/50

Vth 0.42 -0.41 volts

Vjbkd 3.2 -4.1 volts

Ijlk <50.0 <50.0 pA

K' (Uo*Cox/2) 171.2 -36.1 uA/V^2

Low-field Mobility 396.63 83.64 cm^2/V*s

COMMENTS: Poly bias varies with design technology. To account for mask

bias use the appropriate value for the parameters XL and XW

in your SPICE model card.

Design Technology XL (um) XW (um)

----------------- ------- ------

SCN6M_DEEP (lambda=0.09) 0.00 -0.01

thick oxide 0.00 -0.01

SCN6M_SUBM (lambda=0.10) -0.02 0.00

thick oxide -0.02 0.00

FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS

Vth Poly >6.6 <-6.6 volts

PROCESS PARAMETERS N+ P+ POLY N+BLK PLY+BLK M1 M2 UNITS

Sheet Resistance 6.6 7.5 7.7 60.0 316.1 0.08 0.08 ohms/sq

Contact Resistance 10.7 11.3 10.0 4.63 ohms

Gate Oxide Thickness 40 angstrom

PROCESS PARAMETERS M3 POLY_HRI M4 M5 M6 N_W UNITS

Sheet Resistance 0.08 1003.5 0.07 0.07 0.01 929 ohms/sq

Contact Resistance 9.09 13.82 18.56 21.33 ohs

COMMENTS: BLK is silicide block.

CAPACITANCE PARAMETERS N+ P+ POLY M1 M2 M3 M4 M5 M6 R_W D_N_W M5P N_W UNITS

Area (substrate) 954 1168 104 38 19 13 8 8 3 132 132 aF/um^2

Area (N+active) 8533 54 20 14 11 9 8 aF/um^2

Area (P+active) 8271 aF/um^2

Area (poly) 63 17 10 7 5 4 aF/um^2

Area (metal1) 38 14 9 6 5 aF/um^2

Area (metal2) 38 14 9 6 aF/um^2

Area (metal3) 40 15 9 aF/um^2

Area (metal4) 37 14 aF/um^2

Area (metal5) 37 1025 aF/um^2

Area (r well) 937 aF/um^2

Area (d well) 582 aF/um^2

Area (no well) 144 aF/um^2

Fringe (substrate) 267 228 60 55 41 25 aF/um

Fringe (poly) 57 39 29 23 20 19 aF/um

Fringe (metal1) 56 35 23 20 aF/um

Fringe (metal2) 49 35 27 24 aF/um

Fringe (metal3) 53 36 31 aF/um

Fringe (metal4) 60 42 aF/um

Fringe (metal5) 72 aF/um

Overlap (N+active) 806 aF/um

Overlap (P+active) 650 aF/um

CIRCUIT PARAMETERS UNITS

Inverters K

Vinv 1.0 0.75 volts

Vinv 1.5 0.80 volts

Vol (100 uA) 2.0 0.07 volts

Voh (100 uA) 2.0 1.65 volts

Vinv 2.0 0.84 volts

Gain 2.0 -20.24

Ring Oscillator Freq.

D1024_THK (31-stg,3.3V) 341.78 MHz

DIV1024 (31-stg,1.8V) 437.60 MHz

Ring Oscillator Power

D1024_THK (31-stg,3.3V) 0.07 uW/MHz/gate

DIV1024 (31-stg,1.8V) 0.02 uW/MHz/gate

COMMENTS: DEEP_SUBMICRON

T49P SPICE BSIM3 VERSION 3.1 PARAMETERS

SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8

* DATE: Dec 6/04

* LOT: T49P WAF: 4002

* Temperature_parameters=Default

.MODEL CMOSN NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 4E-9

+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.363908

+K1 = 0.5802969 K2 = 3.304956E-3 K3 = 1E-3

+K3B = 2.396754 W0 = 1E-7 NLX = 1.77724E-7

+DVT0W = 0 DVT1W = 0 DVT2W = 0

+DVT0 = 1.3696919 DVT1 = 0.3863182 DVT2 = 0.0111435

+U0 = 270.9714861 UA = -1.376705E-9 UB = 2.283988E-18

+UC = 4.585445E-11 VSAT = 1.233076E5 A0 = 1.9044296

+AGS = 0.4187403 B0 = 3.768681E-7 B1 = 5E-6

+KETA = -7.542091E-3 A1 = 0 A2 = 0.6017329

+RDSW = 105 PRWG = 0.5 PRWB = -0.2

+WR = 1 WINT = 0 LINT = 2.02308E-8

+XL = 0 XW = -1E-8 DWG = -3.807594E-9

+DWB = 1.068482E-8 VOFF = -0.0948017 NFACTOR = 2.1860065

+CIT = 0 CDSC = 2.4E-4 CDSCD = 0

+CDSCB = 0 ETA0 = 2.722866E-3 ETAB = 6.028975E-5

+DSUB = 0.0169785 PCLM = 0.9517499 PDIBLC1 = 0.2819015

+PDIBLC2 = 1.777888E-3 PDIBLCB = -0.1 DROUT = 0.8756738

+PSCBE1 = 1.693724E9 PSCBE2 = 1.087562E-9 PVAG = 0

+DELTA = 0.01 RSH = 6.6 MOBMOD = 1

+PRT = 0 UTE = -1.5 KT1 = -0.11

+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9

+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4

+WL = 0 WLN = 1 WW = 0

+WWN = 1 WWL = 0 LL = 0

+LLN = 1 LW = 0 LWN = 1

+LWL = 0 CAPMOD = 2 XPART = 0.5

+CGDO = 8.06E-10 CGSO = 8.06E-10 CGBO = 1E-12

+CJ = 9.49893E-4 PB = 0.8 MJ = 0.3794582

+CJSW = 2.73954E-10 PBSW = 0.8 MJSW = 0.1405486

+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.1405486

+CF = 0 PVTH0 = -3.287967E-4 PRDSW = -0.7911922

+PK2 = 1.224586E-3 WKETA = 1.156014E-3 LKETA = -8.317948E-4

+PU0 = 5.4645434 PUA = -3.6636E-12 PUB = 0

+PVSAT = 1.281655E3 PETA0 = 5.04222E-5 PKETA = -2.434571E-3 )

*

.MODEL CMOSP PMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 4E-9

+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3723517

+K1 = 0.582664 K2 = 0.025102 K3 = 0

+K3B = 7.8640626 W0 = 1E-6 NLX = 1.119035E-7

+DVT0W = 0 DVT1W = 0 DVT2W = 0

+DVT0 = 0.7283176 DVT1 = 0.2728546 DVT2 = 0.1

+U0 = 103.9954725 UA = 1.104002E-9 UB = 1.966409E-21

+UC = -1E-10 VSAT = 1.627261E5 A0 = 1.8594332

+AGS = 0.4028628 B0 = 3.925957E-7 B1 = 7.24909E-7

+KETA = 0.0255352 A1 = 0.3805726 A2 = 0.3

+RDSW = 314.5914718 PRWG = 0.5 PRWB = 0.0474718

+WR = 1 WINT = 0 LINT = 3.454427E-8

+XL = 0 XW = -1E-8 DWG = -2.154664E-8

+DWB = 7.096045E-9 VOFF = -0.086282 NFACTOR = 1.9157973

+CIT = 0 CDSC = 2.4E-4 CDSCD = 0

+CDSCB = 0 ETA0 = 5.405243E-4 ETAB = -4.331663E-5

+DSUB = 0 PCLM = 1.1570147 PDIBLC1 = 3.444441E-3

+PDIBLC2 = -1E-5 PDIBLCB = -1E-3 DROUT = 0

+PSCBE1 = 9.035097E9 PSCBE2 = 3.439858E-9 PVAG = 0

+DELTA = 0.01 RSH = 7.5 MOBMOD = 1

+PRT = 0 UTE = -1.5 KT1 = -0.11

+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9

+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4

+WL = 0 WLN = 1 WW = 0

+WWN = 1 WWL = 0 LL = 0

+LLN = 1 LW = 0 LWN = 1

+LWL = 0 CAPMOD = 2 XPART = 0.5

+CGDO = 6.5E-10 CGSO = 6.5E-10 CGBO = 1E-12

+CJ = 1.156831E-3 PB = 0.8394653 MJ = 0.4087666

+CJSW = 2.186128E-10 PBSW = 0.8 MJSW = 0.3058017

+CJSWG = 4.22E-10 PBSWG = 0.8 MJSWG = 0.3058017

+CF = 0 PVTH0 = 2.442628E-3 PRDSW = 7.6708227

+PK2 = 2.159356E-3 WKETA = 0.0248885 LKETA = -4.739423E-3

+PU0 = -1.5943037 PUA = -6.13575E-11 PUB = 1E-21

+PVSAT = -50 PETA0 = 8.732925E-5 PKETA = 3.424629E-3 )

*

-----------------------------------------------------------------------------------------------------------------------------

We have tried to design with Kn=342.4µA/V2 and Kp=72.2µA/V2 w.ref to value given in library (K' (Uo*Cox/2) 171.2 -36.1uA/V^2) and threshold voltage Vt also we selected from library as Vth=0.5V and ΔVth=0.08 as we saw in some modes, Vth=0.42V as given below :

------------------------------------------------------------------------------------------------

TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS

MINIMUM 0.27/0.18

Vth 0.50 -0.50 volts

SHORT 20.0/0.18

Idss 602 -306 uA/um

Vth 0.51 -0.50 volts

Vpt 4.7 -5.4 volts

WIDE 20.0/0.18

Ids0 32.5 -29.6 pA/um

LARGE 50/50

Vth 0.42 -0.41 volts

Vjbkd 3.2 -4.1 volts

Ijlk <50.0 <50.0 pA

-----------------------------------------------------------------------------------------------------------------------

We donot know why, after designing, opamp is not working correctly. We designed for UGB = 150 MHz and SR=30V/us for a supply of 0-5V. With this we get only 33Mhz UGB and open loop gain is also only 77dB. Why could this be happening? What change should we make in our design to correct it.

Sizes of transistor we obtained are :

S1=S2=462

S3=S4=11

S5=S8=2

S6=1553

S7=141

Cc = 3pF, Cl=10pF and Ibias=90µA

Where S=W/L. Should we keep L=0.18u or can we keep it as 1u? Also is there a max limit on the width and length of transistors of the library.

Thanks in advance.

Regards,

abdj

- 3rd March 2012, 13:40 #13

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## Re: transconductance parameter

It depends on what you intend: If you want to get a chip fabricated, it's a MUST to get the libraries (actually the full PDK) from that fab/foundry. If you just want to "play around" until you get a working circuit - for educational purpose, or just because of interest in analog design - you could use

__any__(h)spice model library which is publicly available, e.g. from here from the EDAboard, from Berkley, from MOSIS, or from PTM.

Manual calculations provide only a rough approximation to the reality. Simulations take into account many more effects (if the models used provide the respective parameters) and so are indispensable to achieve a working circuit.

For high accuracy analog design -- where good matching is necessary -- always L > Lmin is used (by a factor 3..5), this however trades accuracy for speed: if high UGB is your priority, stay close to Lmin. There are so many dependencies between various circuit specifications; all this analog design stuff is taught in universities and by textbooks, you have to study it.

This is quite usual, as it limits the validity of the models for a certain accuracy. Sometimes several different models are used for various W & L ranges.

- 8th March 2012, 06:17 #14

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## Re: transconductance parameter

Hi Erikl,

Thanks a lot for the info. We were able to design the circuits using the 180 nm library Level 49 ( where Kp= 72.2 µA/V2 , Kn= 342.4µA/V2)

We have another query regarding the noise analysis . Can you please guide us on the steps we should follow to perform noise analysis in Hspice . What all parameters need to be taken in to account( like Af, kf, tnoimod , fnoimod, NLEV, GDSNOI for Level1 ) for the flicker and thermal noise analysis in Level 49 ?

Thanks in advance

Regards,

abdj