Frequency Synthesizer Design

I am using MC145152-2 IC. I have to design it for GSM Frequency (935MHz - 960MHz) The channel spacing is 200KHz.
I am really confused !!!!!!

Is there any online tutorial on how to go about designing it !!!!
Please Help !!!!!!!!
Thanks !!!!!

I am not totally sure but that doesn't look like a fractional PLL, which means your output frequency can only be integer multiples of your input reference frequency. So if you want 200Khz channels you inpur frequency should be 200KHz or something higher which can be divided by the chip(R in this case)). So for your design the divider(N) will vary between 4675 to 4800 for 935MHz to 960MHz.

If you are using this to generate the LO signal then the 200Khz loop bandwidth shouldn't be a problem because you won't be switching your channels that fast.

Also the IC seems very old and doesn't even contain a built-in VCO. Analog Devices makes some great PLL/Synthesizers, have a look at them.

NOTE: I am not sure if the above is even correct, take it with a "bag" of salt. You may be getting better response if this thread was in the RF section.

Thanks a lot.............
That was of great help....
I will post the topic in the RF section

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