VHDL wrapper for FPGA motherboard

vhdl wrapper

Hi,

I'm trying to write a vhdl wrapper to communicate with a Nallatech FPGA motherboard.The board has 2 FPGAs. One to control the PCI interface to the PC(PCI FPGA) and the other is solely for user applications(User FPGA).

The VHDL wrapper i'm trying to implement resides in the User FPGA and communicates with the PCI FPGA interface.I assume that i need to design a FSM to facilitate the communication between both FPGAs.

To test the wrapper, I'll need to use the Nallatech FUSE C/C++ API which sends some data from the PC to the motherboard and retrieves the data back. What components do i connect the wrapper to test a simple data storage in an addressable memory and a dma burst function?

I'm new in this so any advise is very much appreciated.
Please advise.

Justin


The User FPGA have the following port connections to the PCI FPGA:

EMPTY (input)
BUSY (input)
AS/DS# (input)
RD#/WR (output)
REN#/WEN# (output)
INT (output) - not used
ADIO (32 bit Input/Output)
CLK (input)
RST (input)
'#' indicates active low

The communication protocol between the User FPGA and PCI FPGA are as similar to how a FIFO works.
EMPTY and BUSY signals act similarly to fifo_empty and fifo_full signals. The RD#/WR and REN#/WEN# signals combine to give the fifo_ren and fifo_wen signals.

Reading from PCI FPGA to User FPGA
EMPTY signal will go low to indicate there is data to be read. RD#/WR and REN#/WEN# signals will go low after one clock cycle.Data transfer occurs. RD#/WR and REN#/WEN# will go high immediately after the EMPTY signal goes high.

Writting to PCI FPGA from User FPGA
Writting data will occur when RD#/WR is high and REN#/WEN# signal go low. If the PCI FPGA cant receive more data, the BUSY signal will go high.