Interview Questions Related to SET-UP and HOLD Time

setup and hold time equation

Hi All,

Can any body tell me

What are the possible questions on SET-UP and HOLD time for interview.

hold time equation

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Question

write down the famous/basic setup & hold equations.

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Answer

setup equation
Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter

hold equation
Tclktoq + Tlogic - Tskew > Thold

key things to note from above equations
a) once the silicon comes back , if u have setup time problem , u can
increase the clock period (Tclk) to fix it , whereas if u have hold
time problem , its a more serious problem and u will need a new
metal fix tapeout .
b) PLL jitter (Tjitter ) is not used in holdtime equation , since hold
time violation is based on same clock edge . (whereas setup time
vioation depends on 2 consecutive clock edges)
c) above equaitons have clock skew in pessimistic directions . U can play
around with clock skews to get extra margin by skewing them in
favourable direction to decrease violation .
d)from above equations , u can easily answer questions like
"how do u fix setup violations ?" ( faster flop , flop with less setup time , smaller logic between flops , etc ...)
"how do u fix hold violations ?" ( use mindelay flop i.e flop with bigger clock to q , etc ... )
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setup and hold time questions

also you should read the PT report!