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About Native Layer(NT_N) in TSMC Process

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jagadesh

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ic layout native implant

I have couple of Question in mind regarding Native layer.
1. What is Native Layer?How could we(Layout folks) make use of this?
2. Is this a Extra Mask? how and when this would be formed(Is this formed after Nwell, or after diffusion, or..)
3. If this is used for Noise isolation between 2 circuits, Does this provide better isolation than NWELL Ring?

If anyone has some idea on this, pls throw some light, we can discuss.
Thanks
 

nt_n tsmc

Not absolutely sure about this but I think it is a mask to block the N-channel threshold implants. It would be OR'd with the threshold implant mask (not an extra mask layer) and used to form very low threshold nmos (native) transistors.
These are used in transmission gates for example. Since this layer just adds chrome to an existing mask, it cannot be used for any other purpose.
I may be wrong though, as not many designers use native transistors.
 

native layer

Colbhaidh said:
Not absolutely sure about this but I think it is a mask to block the N-channel threshold implants. It would be OR'd with the threshold implant mask (not an extra mask layer) and used to form very low threshold nmos (native) transistors.
These are used in transmission gates for example. Since this layer just adds chrome to an existing mask, it cannot be used for any other purpose.
I may be wrong though, as not many designers use native transistors.
Click to expand...

It is used to block the Pwell implant under the gate of an (Nwell-isolated) NMOS transistor. Hence this Pwell implant = (Pwell andnot Pwell_blocking).
May be the following snapShot helps:
 
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