Help me out to interpret an FPGA spread spectrum code

Hi friends,
This is my first post in this forum.Actually i want some insight into the below mentioned matter

Actually i m into a reengineering project .It is a transmitter which uses spread spectrum technicue . First tjhe raw data bits are FEC encoded(K=7,1/2) .Then its spreaded each bit is multiplied by 1023 bits of the PN sequence. This spreading is done in FPGA . Now each bit of this spreaded code is placed in a 3 bit register and shifte right on each clock pulse . The three bits it uses a index to a lookup table which supplies a total of 252 bits [18 x 14 bits] .These bits are fed to a 14 bit hardware DAC which converts them

I cannot make it out the look up table implementation .Can anybody help in interpreting this

I think it to be a sort of interpolation filter.But if it is how to interpret it .Also the hardware DAC has an 4x interpolation inbuilt in it.

So please help me out how to interpret the look up table implentation.
if needed i will post the code also

Tkanks

see this file
the abstract of this file is:

Increasing interest in ultra-wideband (UWB) communications has engendered the need
for a test bed for UWB systems. An FPGA-based software-defined radio provides both postfabrication
definition of the radio and ample parallel processing power. This thesis presents
the FPGA design for a software-defined radio targeted to impulse ultra-wideband signals.
The system is capable of an effective sampling frequency of up to 8 G-samples/s using timeinterleaved
sampling with eight 1-GHz ADCs. The system is also capable of transmitting
UWB pulses using a transmitter board controlled by the FPGA. In this thesis, the FPGA
design used to capture and export data from the eight ADCs is presented, along with two
systems which make use of the transceiver: a pilot-based matched filter communications
system, and a remote vital signs monitor.