Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

fpga advantage 7.2 - violation due to integer use in VHDl

Status
Not open for further replies.
M

mr_byte31

Full Member level 5
Joined
Oct 19, 2005
Messages
295
Helped
10
Reputation
20
Reaction score
8
Trophy points
1,298
Activity points
3,241
violation in VHDl

hi all
i made an arrat 16 row and size of each row 8 bit.
it will be a rom not a ram so i have no read signal in that block so i intialize them
i tried 2 different codes
subtype elements is std_logic_vector(7 downto 0);
type arr is array (0 to 15) of elements;
signal Arr_data : arr :=(x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00");
Click to expand...

type arr is array(15 downto 0) of std_logic_vector(7 downto 0);
signal Arr_data : arr :=(x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00");
Click to expand...

both of them when i checked them they make violation due to integer use
i want fix that
i use fpga advantage 7.2
any help?
 

violation in VHDl

I don't see any problem with the code. It compiles with &#65ltera Qu&#97rtus.
 

violation in VHDl

i know that there is no error in the code
but when i pressed check button in FPGA Advantage it shows the following
 

violation in VHDl

Did you try to declare the type directly in one step without defining a subtype before?
Code: 
type arr is array (0 to 15) of std_logic_vector(7 downto 0);
It's the usual syntax, I think. Anyway it seems to be a particualr probelm of your tool, I can't help with it.
 

Re: violation in VHDl

FvM said:
Did you try to declare the type directly in one step without defining a subtype before?
Code: 
type arr is array (0 to 15) of std_logic_vector(7 downto 0);
Click to expand...
i did that in my second quote
 

violation in VHDl

I see. So I don't understand the problem. It's legal VHDL, to my opinion. Check the tool documentation for special requirements as version switches or additional libraries.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top