deepu_s_s
Full Member level 5
Hi all,
I am designing ADC in verilog. The first block i need to design is a sampler. The specifications are as follows
Signal frequency : 1KHz
Sampling Frequency : 2Khz
over samppling : 10 % of sampling
So the new sampling frequency is 2.2 KHZ...
Can anyone give some idea how to implement. No code is required.
Replies required asap
Thanks and Regards
Deepak
I am designing ADC in verilog. The first block i need to design is a sampler. The specifications are as follows
Signal frequency : 1KHz
Sampling Frequency : 2Khz
over samppling : 10 % of sampling
So the new sampling frequency is 2.2 KHZ...
Can anyone give some idea how to implement. No code is required.
Replies required asap
Thanks and Regards
Deepak