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Need some help on desing of ADC

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deepu_s_s

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Hi all,

I am designing ADC in verilog. The first block i need to design is a sampler. The specifications are as follows

Signal frequency : 1KHz
Sampling Frequency : 2Khz
over samppling : 10 % of sampling

So the new sampling frequency is 2.2 KHZ...

Can anyone give some idea how to implement. No code is required.

Replies required asap


Thanks and Regards
Deepak
 

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