Can I control the synthesis processing of Synopsys DC

I have a requirement that:
a certain net should have only one trace path in a single timing path.
ex:
for combinational logic F = s ? a: a&b;
I want the net 'a' to have only one trace in a single timing path.

If DC map F to a MUX and a AND, then from 'a' to 'F' there exist 2 trace paths.
I don't want this.

I want DC map 'F' with F = a&(s+~s&b). then from 'a' to 'F' there exists only one trace. From 's' to 'F' there exist 2 trace path, but I don't care that. I only care 'a'. So this is what I want.

I do not mean to force fanout to be 1. I mean all the paths from a certain pin to timing path endpoints, there exist only one trace in a single timing path. Maybe from 'a' there are 100 timing paths. but in each timing path, there is only one trace from 'a' to the timing path endpoint.

Is there any DC commant to control this processing?

Anyone help me?

u can group it ,
then set it to don not touch
set_dont_touch
try it

Hi wkong_zhu,

I assume u still have a chance to change ur RTL code.
what u can do is change ur verilog code style from
F = s ? a : (a&b);

to if-else statement (priority encoder)

or use ur solution
F = a&(s+~s&b);

Hope it works.

Thanks!

But I have tried. With RTL change, it can't achieve what I want.

So I instantiate target library cells directly and set them dont_touch. But there are so many of them, too much work to do.