Question on slew rate of opAmp

It is said that , decreasing the transconductance of input stage will increase the
slew rate of opAmp. So there is the structure shown in the picture. Q3-Q6 are
in fact one split collector lateral pnp. By setting the collector area ration of Q3-
Q6 to be 1:3:1:3, the collector currents and transconductance of Q3 and Q6
are decreased 3/4.
The question is , in my opinion, only 1/4 of the current of current source I3
can be feed to the compensation cap during the slew process. So there is
no increase in slew rate .
I just can not see how the current of I3 is all used to charge or discharge the cap !




Added after 1 hours 9 minutes:

Is it the parastic transistor will make the collector current of Q3 or Q6 equal to
I3 ?

When slewing, just in the transient moment, it can take all the current to load the cap. I would try also with other biasing methods for the input stage, like class-AB biasing

I am sorry , I just can not understand what you mean .
Would you pls explain it ?

fanrourou said:

It is said that , decreasing the transconductance of input stage will increase the
slew rate of opAmp.

Click to expand...

It's wrong. Because slew rate = current flowing threw input pair/Cc. With increasing current the transconductane going up too.

The slew-rate equals the current that flows into a capacitor divided by that capacitor value.

If you have a diff pair as input stage, a known method to have high slew rate is to use emitter degenerated transistors, in that way, for the same current (same SR) you have less gm so you can increase the current without the need of increasing the compensation capacitor.

When the input signal changes rapidly, all the current flows through one branch only, so, I'm guessing that in the 1st drawing all of the current will be used to load the cap while only a fraction is creating gm (something similar to emitter deg).

Another method is to have a class-AB stage, then, the quiescent current (the gm) is small, but the instantaneous current is large so SR goes up a lot.

PaloAlto said:

The slew-rate equals the current that flows into a capacitor divided by that capacitor value.

Click to expand...

You'd better define exactly what current and what capacitor you mean. Anyway, if you suppose compensation capacitor and tail current it is true.

PaloAlto said:

If you have a diff pair as input stage, a known method to have high slew rate is to use emitter degenerated transistors,

Click to expand...

I'd appriciate it, if you gave the sources if this. thanks

PaloAlto said:

in that way, for the same current (same SR) you have less gm so you can increase the current without the need of increasing the compensation capacitor.

Click to expand...

In a dif pair the current is seted by tail current transistor and it means that one way to change current flowing threw a dif pair is to change tail current source.
By the way, Slew Rate is a Large Signal parameter, gm - small signal one that is why it is not absolutely correct to try find any ratios between them. And with increasing compesation capacitor slew rate is decreasing!

PaloAlto said:

When the input signal changes rapidly, all the current flows through one branch only, so, I'm guessing that in the 1st drawing all of the current will be used to load the cap while only a fraction is creating gm (something similar to emitter deg).
Another method is to have a class-AB stage, then, the quiescent current (the gm) is small, but the instantaneous current is large so SR goes up a lot.

Click to expand...

It is it not clear what are you talking about. I'm sorry...

What PaloAlto describes makes sense to me. The best way known to designers to increase the slew-rate of the opamp is to decrease the input-stage transconductance. Once can do that by emitter-degeneration or just by throwing away some current (as shown in the first schematic) or by using devices with poor gm. That is why you see fet input devices have greater slew-rates compared with bjt for the same current. Invariably you'll find that all the Bi-FET opamps employ a FET input stage and this is not only for their 'no-bias-current' property.

**broken link removed**

Okay ,everyone ! Think about what I am asking, and what the nonsense answer you give. I am so regret about you .
I maybe find the anwer .
In the book <the art of analog layout>, It is said that the lateral pnp transistor
has a property that, when one collector of the split collectors is saturated, the
re-inject current ( because the collectorr pn junction is forward conduct) will
be collect by the other collectors (not saturate) . So , during slew process, by my guess, for example, Q3-Q4 are cut-off, Q5 is in linear region, Q6 is in saturate
region, then the re-inject current by the collector junction of Q6 will be collected
by Q5. If Ic of Q5 is not changed, then the tail current of I3 will all flow to the Q6.

saro_k_82, I haven't seen anything in this article. You haven't make right conclusions. I can suggest that you were confused by eq.20. Unfortunately, author mixed up the causes and the consequences. Actually, when you decrease gm in eq.(20), the gain-bandwidth product from (15) decrease too and again according to (20) dV0/dt do not change because when you decrease gm, bandwidth go down too. Anyway, you can make some simulations with simple two stage opamp.

yxo said:

saro_k_82, I haven't seen anything in this article. You haven't make right conclusions. I can suggest that you were confused by eq.20. Unfortunately, author mixed up the causes and the consequences. Actually, when you decrease gm in eq.(20), the gain-bandwidth product from (15) decrease too and again according to (20) dV0/dt do not change because when you decrease gm, bandwidth go down too. Anyway, you can make some simulations with simple two stage opamp.

Click to expand...

You are not taking in to account the increase in the tail current. Operating with lower gm devices (or structures) allows you to increase the current without altering the UGB( and therefore Cc). Slew-rate is ultimately I/C right?

yxo said:

You'd better define exactly what current and what capacitor you mean. Anyway, if you suppose compensation capacitor and tail current it is true.

Click to expand...

That is true only with a two stages amplifier with a miller or parallel compensation capacitor. If you have an OTA (one stage only) SR equals the current that can flow into the load cap divided by the cap value. Moreover if your input stage is not a diff pair, then the SR is not the tail current. It is very important to understand that if you want to maximize SR.

yxo said:

I'd appriciate it, if you gave the sources if this. thanks

Click to expand...

I don't really have sources for that, it is just adding a resistance at the emitter (source) of the active transistors. You can see a little here: https://en.wikipedia.org/wiki/Common_emitter#Emitter_degeneration For a diff pair is just the same.

yxo said:

Slew Rate is a Large Signal parameter, gm - small signal

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That's the key point! You can break that correlation. Keep the small signal parameter (quiescent current) while increasing the large signal one, for example with class-AB

yxo said:

PaloAlto said:

When the input signal changes rapidly, all the current flows through one branch only, so, I'm guessing that in the 1st drawing all of the current will be used to load the cap while only a fraction is creating gm (something similar to emitter deg).
Another method is to have a class-AB stage, then, the quiescent current (the gm) is small, but the instantaneous current is large so SR goes up a lot.

Click to expand...

It is it not clear what are you talking about. I'm sorry...

Click to expand...

saro_k_82 has explained it already.

fanrourou said:

So , during slew process, by my guess, for example, Q3-Q4 are cut-off, Q5 is in linear region, Q6 is in saturate
region, then the re-inject current by the collector junction of Q6 will be collected
by Q5. If Ic of Q5 is not changed, then the tail current of I3 will all flow to the Q6

Click to expand...

I am not 100% sure that I understand you, but I think so and I think you are right. In quiescent situation the tail current is divided by four, so gm=Itail/2Vt. But, when slewing, the current that can flow into the cap is the whole Itail, so SR is twice that of a diff pair with the same gm.

BTW. I really don't think we are talking nonsense here. I find the answers quite appropriated to your question 8)