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how to finish such a by-4 divider without reset

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trashbox

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I need to divide a clock(freq=200KHz, duty cycle is 40~60%) by 4 without reset signal. This clock is IN at the attachment and the desired output is OUT at the attachment.

Many counter need a RESET control signal. If no RESET is available, How can I realize such a function? Thanks!

Best regards
Trashbox
 

Why do you think, the counter needs a reset signal? It doesn't. If it starts with an arbitrary count a power on, it will emit the first output pulse after 0 to 3 counts. In simulation, it may need an initial value (not necessarily a reset), otherwise the output stays at "X" state permanently, a real counter has no "X" state.
 

just to add a few words.
FvM is complete correct - no reset is really necessary. actually in some applications it is recommended to do it without a reset! (because the clock might only be available in a later stage and the asynch reset removal is aligned with a reset synchronizer to the clock edge)
but if you use a counter and no reset make sure you have no forbidden states - i.e. try using binary counters but not ring counters or johnson counters since they might "wake up" in a forbidden state (or include a recovery circuit).

ND
https://asicdigitaldesign.wordpress.com/
 

Hi FvM!
Thanks for your reply. If no RESET, how can you set the initial value? Just as you said, if no initial value is assigned, the output stays at "X" state permanently.

Regards,
Trashbox
 

Yes, true.... the simulator will show you a X (unknown) , so you must somehow set a state to the counter, in reality , the counter will count. If no reset, you can divide simply with an AND gate between (LSB)bit and (LSB+1)bit...
 

A simulator allows to set an initial state. The syntax is different with HDL languages. Also hardware logic (e. g. FPGA or CPLD) mostly have an implicite power-on reset to an initial state. As an example a VHDL signal definition:
Code: 
SIGNAL cnt: UNSIGNED(1 DOWNTO 0) := "00";
It defines an initial state in simulation and a power-on reset (if available in the respective logic family) in synthesis.
 

Hi dexter_ex_2ks and FvM!
Thank you for your kindness. I'll try it.

Best Regards,
Trashbox
 

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