About the two-stage opamp design procedure

Hello, everyboody!

I doubt my design procedures of a two-stage Opamp, so I described these procedures in below and invites everybody point out the mistakes. thanks!

If the specification of the Opamp (like DC gain, Unit-gain bandwidth(Wu), phase margine and slew rate) is chosen:
step1: Design the transistor sizes to achieve the appropriate DC gain for this Opamp if the DC bias current is chosen.
step2: Calculate the second pole frequency (Wp2=gm,out/CL) to demonstrate whether the Wp2 is equal to the 2*Wu. If the Wp2 is equal to the 2*Wu, we can ensure the phase margine is equal to 63 degree.
step3: Becaue of the Wu and gm,input is obtained, we can use the equation Wu=gm,input /Cc to determine the compensated capacitor(Cc) values.
step4:Calculate the slew rate(SR=Id,input/Cc) to demonstrate whether the SR is to fit the specification. If the SR is not to fit the specification, we need to redesign the Id,input.
*gm,input is the transconductance of the input differential amplifier.
gm,out is the transconductance of the output common-source amplifier.
Id,input is the total DC current of the input differential amplifier.

It seems like a good procedure.

Although I doubt the way you achieve your input gm. This is the main source for offset and noise. So if you design for these parameter you need to take them in the loop.

Two points, do not concentrate on one spec ONLY, because you will be in trouble, try to do all of it at the same time.
Try to get a feel for each parameter, meaning that change each parameter and monitor the output. Then try to justify the results. Now try to get the desired output by changing the parameters.

I think there is no recipe, I wish there was, but there is not. The input caps are important and affect the bandwidth.