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* Connectivity based on flight-lines
* Memory placement over the boundary
* Optimal placement of macro's or 3 rd party I.P's
* possible distance between analog macros and high switching digital blocks, to reduce noise.
* optimal placement of padring's considering, SSN, power-pads location
* power budgetting, planning, network
* Timing driven floorplan
* Determine the location of large block
* Macro placement, such as RAM, HardIP, analog block ...
* Determine the location of IO pad
* Power topology selection
One more point to be taken into consideration is to make the std cell placement area as uniform as possible so that u will get equal amount of routing resources, and proper creation of blockages near the macro corners and in a narrow notches to avoid congestion.
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