Xilinx S3E starter kit (Intel strataflash read/write)

As shown in Figure 5-1, the four LCD data signals are also shared with StrataFlash data
lines SF_D<11:8>. As shown in Table 5-2, the LCD/StrataFlash interaction depends on the
application usage in the design. When the StrataFlash memory is disabled (SF_CE0 =
High), then the FPGA application has full read/write access to the LCD. Conversely, when
LCD read operations are disabled (LCD_RW = Low), then the FPGA application has full
read/write access to the StrataFlash memory

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rishiric said:

Hi everybody,

I am working on a project in which I need to store my data in Intel strataflash memory. (FYI: I am using Xilinx Spartan 3e Stater kit). My verilog code performs the following operations in a sequence.

Block Erase -> Byte program -> Status register check -> Read byte (same address)

But It looks like It is not writing at all. because even if I program different data at different time, the code reads the same data which does not match with the written data.
I would appreciate if somebody has already done this task and he would like to share some thoughts about it.

I have attached the FSM and a verilog code with this.

Urgent help needed.
Thanks in advance.

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