Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how the clock latency influences timing in the STA

Status
Not open for further replies.
O

owen_li

Full Member level 3
Joined
Jul 22, 2007
Messages
150
Helped
17
Reputation
34
Reaction score
15
Trophy points
1,298
Activity points
2,301
I wonder tthat how the clock latency influences the timing.

In my opinion, if clock latency is worse. Then all the arrival time of the clock will be delayed equally to the register clock pins. So which aspect will be worsen when
the clock latency is worse. Thank you very much!
 

note that clock skew has 2 components
- structural skew
- PVT skew

as you increase clock tree delay and balance it , structural skew is Okay,but
PVT skew becomes worst . i.e more buffers in clock path will have more
more variations in PVT (Process , Voltage , Temperature) and hence skew
increases.

some people call PVT skew as OCV (on chip variations)
 

clock latency matters in STA for sure but its effect is different from that of clock skew. li's answer that clock latency matters since it worsen the hold time. It is more like it. But for which flip-flops and under what conditions? Other effects of clock latency? when it is going to worse the setup time?

I put my two-cents in my blog.
**broken link removed**
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top