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PLL phase detect output and output phase error plots

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robismyname

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I'm using ADIsimPLL to help quantify my preliminary design of a fractional-N PLL. I ran through the tutorial and compared their graphs to my graphs. Every thing looks similar except for the phase detect output graph and the output phase error graph. Can someone look at my graphs and tell me if it makes sense? I cant interpret the graphs.
 

-Phase detector output seems normal.If you zoom in the waveform you will see phase error between reference and input signal differences..
-Output Phase Error seems also normal but lock detect has arrived very rapidly to locking-in state that is a little bit strange..

I think you should zoom-in the graphs to interpret them.
 

BigBoss said:
-Output Phase Error seems also normal but lock detect has arrived very rapidly to locking-in state that is a little bit strange.
Click to expand...

lock detect seems strange because I didn't enable the lock detect component in ADIsimPLL, now i set it to Analogue OD.
 

Graphs seems reasonable.
Freq goes up to 2.4GHz in 60 us, the freq error is simply the difference between your target freq and your actual freq, phase error goes to zero in 100us.


I hope this can help.

Mazz
 

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