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How to use IBIS model in a VHDL Project?

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mehrara

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hi
I have a vhdl project in ISE. I use Cypress's CY68013 USB transciver and the only model available for it in cypress.com is IBIS. How can I simulate my design ?(in modelsim)

Thanks...
 

You don't.

IBIS models the analog voltage rises, swings, overshoots and so on. It is for simulating the analog connection of your traces, to detect reflections and mismatches.

IBIS doesn't know or care about the functionality: the meaning of the '1' and '0' sequences coming out of the chip, it only models HOW a '1' or '0' looks like in the analog domain (SPICE).

What you need is a bus functional model for the chip that communicates to your VHDL design.

Please explain your entire design, so we can see what communicates with what, and what exactly you need the Modelsim simulation for...
 

I want to build up a high speed connection between FPGA and computer. I chose USB and I want to use Cypress`s CY68013 USB transciver. In order to test my design I want to do Post place and route simulation in ModelSim. What can I do?

Thanks
p.s. I think the functionality of the IC is too complicated to write a functional model for.
 

Check
**broken link removed**

They offer a testbench in VHDL which is similar to USB transceiver.
 

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