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Regarding Via in layout

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AdvaRes

AdvaRes

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Hi all,

Can someone tell me how to connect:
Metal 2 to metal 1 (case 1 fig),
Metal 2 layer to Metal 1 layer than to polysilicon (case 2) ?
Metal 2 to Polysilican (case 3 fig)
I knwo that we use Via but I dont know which Via to use since there is Via1, 2....

Any exemple will be very welcommed.

Thanks.
 

1 via 2

2 stack via 2 and via 1 if possible. otherwise space via 1 and 2

3 usually not possible. You can first go to metal 1 with via 2 and then go to the poly layer with via 1
 

Hi,

Via 1 -> which conncts M1 to M2

Via 2 -> which connects M2 to M3

Via3 -> which connects M3 to M4

and so on.

One via which named as CO which will connect M1 -> poly
or M1 -> OD

depends on which layer is below the M1


Regards,

Analayout.
 

Thank you drDOC and analayout,

I agree with you analayout Via 1 is used to connect M2 to M1. My problem is that Virtuoso shows this error message


Rule VIA1X.LO.1: Minimum number of VIAiX inside {VIAiX upsized by 30.0um}: 10

Also, When I zoom out I get a Vertex Polygon arround my layout (a very big square )

-29.115 , -29.18
30.985 , -29.18
30.985 , 30.92
-29.115 , 30.92

Could someone explain ?
 

Hi AdvaRes,
Some times,The number of vias required is also depend on technology and process. So i think please check your process.
 

Hi AdvaRes - I guess the process is indicating that if you are using a wide metal then some process need a multiple rows of vias i.e 10X10 VIA's or maybe that you need a large size of vias but normally large sized VIAs are used in bondpads or IOPADS.

I would suggest that if you used wide metal make a multiple rows and columns of vias, also you can make you wide metal i.e multiple of 4microns wide or so.

Then hopefully your DRC problem will be gone.

I hope this help.

Cheers

AdvaRes said:
Thank you drDOC and analayout,

I agree with you analayout Via 1 is used to connect M2 to M1. My problem is that Virtuoso shows this error message


Rule VIA1X.LO.1: Minimum number of VIAiX inside {VIAiX upsized by 30.0um}: 10

Also, When I zoom out I get a Vertex Polygon arround my layout (a very big square )

-29.115 , -29.18
30.985 , -29.18
30.985 , 30.92
-29.115 , 30.92

Could someone explain ?
Click to expand...
 

    AdvaRes

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
AdvaRes said:
Thank you drDOC and analayout,

I agree with you analayout Via 1 is used to connect M2 to M1. My problem is that Virtuoso shows this error message


Rule VIA1X.LO.1: Minimum number of VIAiX inside {VIAiX upsized by 30.0um}: 10
Click to expand...

Hi,

I also met the problem Rule VIA1X.LO.1. I finally solved. So I want to share it.

I solved it because there is some connection missing between two layers of metal, instead of the explanation of the rule.
 

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