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Questions about ECOs and analyzing the timing reports in STA

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energeticdin

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Hi all,

I come across one question?
1. In STA, if we find some of the cells which i need to upsize?
After upsizing the cells, if the timing get even worse?
What may be the reason?

2. While upsizing the cells, what are the things we need to take care?
whether we have to see previous cell transition and their fanout values?

3. What are the ways we can suggest layout team to fix the violation, i,e in STA when analyzing the timing reports?
Whether we can also consider the follwing reason?
1. Checking skew
2. Cells to upsize
3. net length between two cells.

Give me some more suggestion

Din
 

+timing reports .rpt

Hi Din:

1. The transition at the input pin would have worsened since by upsizing the cell the input cap increases which could load the previous cell (low drive) and would caused a timing degradation.

2. we need to see the i/p transition and output load. i/p tran could be high because the load on the previous cell is high or either the i/p tran on the previous could be high depends on the situation. Based on the situation u can fix the required

3. During post-route .based on the required scenario we can either upsize , downsize, insert buffer or skew the clock . But one should also take care of physical locations.
 

sdc file multimode

Thanks kssai,

Is ther any ECO flow?
What is Multi mode/Multi-vt designs and timing closure?

Plz tell me about this concept?

Din
 

sign-off corners

Hi Din :

ECOs are generally iterative in nature. As said in the previous post one need to look into the timing report and see whether to size the cell up or insert buffer or clone all depends on the situation. Generally its always better to try out with the required changes is there any improvement in the sign-off tool (in many case its PT). If its positive one need to do an ECO and incremental route in-order to route the new cell and repair some of the DRC caused because of this. Then again one has to perform extraction and run timining analysis and check for any viokations and fix them again (start from first). The loop goes many a times depending upon the timing violation and quality of ECOs applied.

Multi Mode approach is generally used if you have many sign-off corners to close on. So the tool makes sure it satisfy constraints in each and every mode in the design with the corresponding SDC thereby enabling a faster timing closure (reduced no of ECO cycles)

Muti-Vt design is a low power approach. Here we have HVT , LVT and normal VT cells. If you r more worried aout leakage u use the HVT but ur timing would degrade. LVTs are leaky but faster. So based on whether timing or power one has to choose between the two.

Regards,
sai
 
Re: Reg: STA

Thanks a lot kssai

Suggest some books to learn and analyze timing reports deeply.

Thanks
Din
 

Reg: STA

Hi Din,

If you are using Prime-time for STA, it has an utility called, "eco_fix_violations.tcl". It will optimally upsize/down-size the cells inorder to fix the timing. Use this eco'ed netlist for P&R and manually place the cells near to each other for the rest of the violated paths.

This is how we did and observed positive results.

Good luck.
 

Re: Reg: STA

Hi Sunil,

Thanks.
Where will be eco_fix_violations.tcl available in PT.

Din
 

Reg: STA

Hi Din,

U can search in Solvnet articles for "eco_fix_violations.tcl".

I am having that file but not sure whether we can share this file here or not. Pls. search for Solvnet articles.

However, the flow for this in PT is as follows.

In the
first iteration:

update_timing
report_constraint -all_violators -verbose > ./reports/cons_viol_pre_eco.rpt
source ../../sdc/eco_fix_violations.tcl
eco_fix_violations -max_delay -verbose -output reports/eco_fixes.rpt
report_constraint -all_violators -verbose > ./reports/cons_viol_post_eco.rpt

Now PT will generate a log file with corresponding possible fixesafter resizing the cells. "cons_viol_post_eco.rpt" is the timing report after after resizing the cells. One point here it is analysis only. You only need to implement the resizing of the cells in the second iteration.

source -echo ./eco_fixes.rpt this report will have the re-sizing of the cells)
source -echo ./<SDC file>
set_propagated_clock [all_clocks]
update_timing
report_constraint -all_violators -verbose > ./reports/cons_viol_pre_eco.rpt
source ../../sdc/eco_fix_violations.tcl
eco_fix_violations -max_delay -verbose -output reports/eco_fixes.rpt
report_constraint -all_violators -verbose > ./reports/cons_viol_post_eco.rpt

Now again verify the post_eco timing reports. If u observe any good results, go ahead for the next iteration by sourcing the latest "eco_fixes.rpt" file in the next iteration.

U iterate the procedure till "eco_fixes.rpt" file exhausts and no resizing of the cells are updated into that file.

Now u provide the Final netlist to your P&R tool for further fixes if any.

In our care we've observed fruitful results with this procedure.

Good Luck and pls. let us know if it worked for u.

Regards,
SunilB.
 

Re: Reg: STA

energeticdin said:
Hi all,

I come across one question?
1. In STA, if we find some of the cells which i need to upsize?
After upsizing the cells, if the timing get even worse?
What may be the reason?

Din

Not so familiar with STA, however if sizing cells to adjust timing, the whole path needs to be considered. A logic effor point of view should help better with this.
 

Re: Reg: STA

Hi Sunil,

I tried in Goldtime.
I uploaded netlist and SPEF.

After update_timing,

Source eco_fix_violations.tcl

But its giving some warning.

I tried ur way of explanation.

Plz let me know.

Din
 

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