[Help] Problem with onboard regulator

Hey guys, I got a scenario during power down where my design still have VCCIO (3.3V) stay above my inverter's VIL level. This has translated into my chip is still power on.

I have no idea on board design. Does this scenario hold true? How would the industry spec their power supply rail in term of power level? i.e for 3V-3.6V where <3V can be considered as power off. The client side or my side need to make sure VCCIO is <3V?

Thanks in advance.

Quite often this is because some inputs or outputs of your circuit are connected to other circuitw which are still powered. Since CMOS parts have input diodes to Vdd, if one of those inputs is high it will power your circuit through one of the protection diodes. To avoid this you need to either disconnect all the inputs using say bus switches or make sure they are always low (impractical).

Often the circuit which is supposed to be off will actually run while being powered through one of its inputs. It has nothing to do with the cap discharging slowly or the regulator not shutting down properly.

So to really solve the problem, use bus switches, driven by the same signal that disables your power supply. An example of bus switch is the 74CBT3245.