How to simulate Bandwidth of lvds driver?

ac analysis for bandwidth

Dear all:

I am designing a 600MHz of lvds IO, but i don't know how to simualte the bandwidth of lvds driver, could anyone can help me?

My structure like the attached file.

Thanks for your help.

mpig

lvds driver circuit

That's a good question. You could simply do an ac analysis differentially and get the BW from the bode plot. I think that although the signal excursion is large. You should be able to get a good estimation of the bandwidth. I would anyway always do a transient analysis, put a 600MHz signal and see if it goes through it.

Now I also have a question, what are you doing with the CM? What is the bandwidth of the cm loop going to be? Also 600MHz?

lvds driver ac analysis

Dear PaloAlto:

The attached file is my reference, I will use bandgap and unit gain buf to set CM.

The BW of opa is smaller than 600MHz. (I will reference the database of opa).

I have questions,too.
==>Do you mean I needs to combine CM circuit and the driver circuit to analysis BW?
==> when we use ac analysis to simulate BW of circuit, it needs a CM voltage on input, than "ac 1" to analysis AC performance. But the differential inputs are full scale of vdd for driver, does the result of bode plot believable?

mpig

mpig09,

You have to consider the bandwidth of the cm and the diff mode part separately. I asked you about the CM BW because I am really interested on it. I think that you should have a BW for the cm part as large as the diff BW. But I personally didn't do that to save power.

Now, about the bandwidth, you have to do two things:

* First check the predriver. Do transients to either find its BW or make sure that is large enough for your 600MHz.

* Then, take the output part of the driver (the circuit you show in the pic) and bias it in half way operation (with a zero diff signal approx). Include R and Cloads. Try to do an ac analysis on that to see the BW. I think it should be possible. If it doesn't work, you can calculate an approximation. Take the time constant formed by the 50 ohm resistor (to the ac ground) and Cload (leave that one as a parameter). consider at least 4 taus (that sounds reasonable for an lvds output) and 1/ that gives you the max freq. For 2pF it is 1.25GHz. for 5pF 500MHz, 10pF 250MHz.

You can also do it the other way around, for 600MHz, the period is 1.6ns, if you wnat to be settled in say half clock pulse, then you have 400ps to settle. The max Cload that can resit that is less than 4pF.

Just remember that Cload includes everything! Parasitics of the output transistors, the pads, bonding wires, pins, PCB traces.

BTW you can always do parametric transients while increasing the freq. That gives you the large signal BW