Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to separate a string of data into even and odd data?

Status
Not open for further replies.

m.zihanul

Newbie level 5
Joined
Oct 8, 2008
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,340
hi, i'm new with vhdl coding (one week experience).
how to separate a string of data into even and odd data?
is it the same as c language or there are any better ways?

hope there are someone here that can help me.

thanks
 

Welcome to the real world.(of concurrency)

what is the condition on which you want separate the two data streams?
e.g. if you want to separate them on each clock edge...
you can have a bit counter (a T flop) and use its output as select line to a 2:1 multiplexer. At every odd transition you can separate the data.

else just connect your signal generated to produce your condition to the select line of the mux.
while learning a HDL It is a good practice to have an idea of the hardware which is going to be synthesized because of your code.Once you know the hardware..coding is a piece of cake.you can refer to any text book on VHDl.(I don't want to spoil your learning experience)
Happy coding.
 

thanks for the reply

i want to separate them on each clock edge.

actually i want to do a QPSK modulation. so first thing i have to get done is to divide the PCM into dibits formation that are at even and odd bit.

i still cant figure out a good solution for the coding. if only you could give me an easy example or a good books that i can read.

anyways thank you very much for the reply.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top