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How to verify Netlist and SDC file ?

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seeravi

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hi,

1). for Physical design start these are the files we get input from Synthesis Team.
1)Netlist,
2)SDC.

before starting the physical design flow, how to verify NETLIST and SDC file is correct or worng and inside the NETLIST if any assign statement we go back to Synthesis Team or any other method is there ?

2).what are the information to check the NETLIST and SDC file once we get?

plz reply\

Regards,
Ravi.
 

netlist,sdc

There are some unix commands please check the manual u wil get it and if there are any buffers then u have to remove it by using set_do_assign --on smething like tht please check soc user guide i hopeu will find one

Reply me

Added after 32 seconds:

Read timing closure its given in tht
 

Re: netlist,sdc

my 2 cents,

After receiving database from synthesis team and prior to place and route you can perform some sanity checks.

1. To validate the quality of constraints read in the netlist and the sdc file in the primetime and perform check_timing and generate report which will giving inputs like the quality of database like how many of the flip flops are getting clocks, how many flops are constrained, how many ports are having constrained or whether there is any violation like that which will surely give some idea about the quality of the delivered database.
2. In order to understand the quality of the database interms of timing , generate timing reports and understand the quality of timing how good or how bad is the database and how much you can optimize at the backend or at the placement and routing stages or what paths you cannot meet timing even during placement stages
3. After analying bit on the timing reports you can get some idea of what all areas you need to close pack during placement so that you can create regions.
4. Generate report_area and report_references -hier report in the designcompiler or synthesis stage to better understand the design hierarchy.
5. try performing formal verification using rtl 2 synthesized gates to know whether the design after synthesis stage is meeting formal verification requirement.

There is a good document on 3 rd party delivery , i believe it will be of some use
https://www.vlsichipdesign.com/3rd_party_IP_delivery.html

best regards,

chip design made easy
https://www.vlsichipdesign.com
 

Re: netlist,sdc

vlsichipdesigner said:
my 2 cents,

After receiving database from synthesis team and prior to place and route you can perform some sanity checks.

1. To validate the quality of constraints read in the netlist and the sdc file in the primetime and perform check_timing and generate report which will giving inputs like the quality of database like how many of the flip flops are getting clocks, how many flops are constrained, how many ports are having constrained or whether there is any violation like that which will surely give some idea about the quality of the delivered database.
2. In order to understand the quality of the database interms of timing , generate timing reports and understand the quality of timing how good or how bad is the database and how much you can optimize at the backend or at the placement and routing stages or what paths you cannot meet timing even during placement stages
3. After analying bit on the timing reports you can get some idea of what all areas you need to close pack during placement so that you can create regions.
4. Generate report_area and report_references -hier report in the designcompiler or synthesis stage to better understand the design hierarchy.
5. try performing formal verification using rtl 2 synthesized gates to know whether the design after synthesis stage is meeting formal verification requirement.

There is a good document on 3 rd party delivery , i believe it will be of some use
https://www.vlsichipdesign.com/3rd_party_IP_delivery.html

best regards,

chip design made easy
https://www.vlsichipdesign.com
Click to expand...





ur information is very useful
 

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