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Does anyone know how to verify CDR circuit?

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givensoo

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verify cdr

For it involves analog PLL,so makes it hard to verify.I want to know: have any tools to verify the mix-signal system?
Now i have Specman E and Hsim,can i just put the hspice netlist into verilog netlist and then put the analog block into Specman E environment to do the verification?dose any one kown how to make it? pls help me....
 

If you using Cadence tools............... better to raise Service Request..........
They will give the solution.
 

Hi,
For Mixed Signal Simulations tools are available from Cadence and Synopsys.
For Cadence IUS8.1 onwards you required separate AMS license, it requires total of 8 tokens. With this setup you can simulate the Analog and Digital designs (For analog either SPICE Netlist or Analog Models implemented in Verilog/VHDL-A plus Digital Verilog/VHDL-D is required). I dont know whether SystemVerilog has a Analog version.
Synopsys also has AMS tool in Scirocco, details I dont know check with any of the Synopsys AE.

(I'm totally ignorant the challenges in interfacing digital and analog interfaces)

-Paul
 

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