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  1. #1
    Full Member level 3
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    vhdl shift register

    hi guys,

    im newbie in VHDL. i have assignment to write left shifting shift register in dataflow model. here is the code tht i need to change it to dataflow model:
    ----------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity shift_register is

    port( d:in std_logic_vector (7 downto 0);
    ldsh: in std_logic;
    en: in std_logic;
    w: in std_logic;
    clk: in std_logic;
    rst: in std_logic;
    q : buffer std_logic_vector(7 downto 0));

    end shift_register;

    architecture shift of shift_register is

    begin
    process (clk,rst)
    begin


    if rst= '0' then
    q<= (others=>'0');
    elsif (clk'event and clk='1') then
    if en='1' then
    if ldsh='1' then
    d(0)<=0;
    q<=d;
    else
    q(0)<=w;
    for i in 1 to 7 loop
    q(i)<=q(i-1);
    end loop;
    end if;
    end if;
    end if;
    end process;
    end shift;
    ------------------------------

    •   Alt2nd October 2008, 07:17

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  2. #2
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    shift register vhdl

    Your way is fail.
    In VHDL you don't need to use the loop!
    That's the solution:
    ibrary ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity shift_register is

    port(
    clk : in std_logic;
    rst : in std_logic;
    d : in std_logic_vector(7 downto 0);
    ldsh : in std_logic; -- load parallel?
    en : in std_logic;
    w : in std_logic;
    q : buffer std_logic_vector(7 downto 0)
    );

    end shift_register;

    architecture shift of shift_register is
    signal int_reg :std_logic_vector (7 downto 0);
    begin

    q <= int_reg;

    process (clk,rst)
    begin


    if rst= '0' then
    int_reg <= (others => '0');
    elsif (clk'event and clk='1') then
    if en='1' then
    if ldsh = '1' then
    -- d(0)<='0'; -- ???? I've not understood what you wanna do,
    -- but this assignment is an error in vhdl,
    -- you cannot assign something to an input pin
    int_reg <= d; -- parallel load (ok)
    else
    int_reg(7 downto 1) <= int_reg(6 downto 0);
    int_reg(0) <= w;
    end if;
    end if;
    end if;
    end process;
    end shift;

    ------------------------------------------------------------------------------------


    The only question is about what you wanna do on ldsh='1' I mean ok it's a parallel load of the register, but what you wanna do when you've written d(0) <= '0'



    •   Alt2nd October 2008, 15:52

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  3. #3
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    shift register in vhdl

    library ieee;
    use ieee.std_logic_1164.all;

    entity basic_shift_register is

    generic
    (
    NUM_STAGES : natural := 64
    );

    port
    (
    clk : in std_logic;
    enable : in std_logic;
    sr_in : in std_logic;
    sr_out : out std_logic
    );

    end entity;

    architecture rtl of basic_shift_register is

    -- Build an array type for the shift register
    type sr_length is array ((NUM_STAGES-1) downto 0) of std_logic;

    -- Declare the shift register signal
    signal sr: sr_length;

    begin

    process (clk)
    begin
    if (rising_edge(clk)) then

    if (enable = '1') then

    -- Shift data by one stage; data from last stage is lost
    sr((NUM_STAGES-1) downto 1) <= sr((NUM_STAGES-2) downto 0);

    -- Load new data into the first stage
    sr(0) <= sr_in;

    end if;
    end if;
    end process;

    -- Capture the data from the last stage, before it is lost
    sr_out <= sr(NUM_STAGES-1);

    end rtl;



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