How to best design high frequency ADC in 0.13um BiCMOS process?

Hi, I am trying to design an ADC with 8bit 2GS/s specifications with minimum power consumption. The process is 0.13um BiCMOS. I am trying to look for papers and found some groups used folding+interpolation to achieve >1G with 8bits resolution. Is F+I the only possible way to achieve the specs or there are better ways to do it? Do anyone have some reference for me please?

Thanks!

Re: high freq ADC design

Here some scaling rules to consider:

A flash scale by a base of 8!!!

P(flashADC)~8^n

Why?. Number of comps by 2^n. The area of each by (2^n)^2=4^n.

You can consider ADC process as weighing using unprecise weights and a noisy balance. If you make a binary decision which weight replace you can make errors as long the scale ratio between the weights is less than 2. That tolerates also noisy decision. After log(resolution)/log(radix) steps you arrive with an esemble of weights. If you know all the numbers of the weights you are done.

The most efficient architecture is the SAP. You need one comparator and minimum steps. But you should dimensioning the caps not on matching! Then:

P(optimumADC)~n

The excercises are currently in work in industry and academic research.