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Explain me this Total Leakage Power

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cafukarfoo

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Hello Sir/Madam,

I run a design both in 400KHz and 1.1MHz clock constraint.

For design constraint in 400kHz,
total leakage power = 2.7uW

For design constraint in 1.1MHz,
total leakage power = 0.7 uW

Can anyone help to explain this? THanks.
 

Re: Total Leakge Power

Can you give the area of the different synthesis ?
 

Re: Total Leakge Power

Gate area is the same.

Both design have the same floorplan.

Everything same expect the clock constraint is higher for the other one.
 

Total Leakge Power

If the designs are exactly the same then the leakage must be the same. You should check to see what library cells are used...sounds like one has a higher VT so you have lower leakage, but it is unusual for it to be the faster one.

Are you sure these are not dynamic power numbers?
 

Re: Total Leakge Power

Hi,

Can you give the total number or percentage of high vt, low vt and regular vt cells used in both the iterations?

As low vt cells will have higher leakage and less dely while high vt cells will have low leakage and higher delay, pls examine the delay and leakage of different vtcells in your library.

It may help to find out the answer.

Thanks..

HAK..
 

Re: Total Leakge Power

cafukarfoo said:
Hello Sir/Madam,

I run a design both in 400KHz and 1.1MHz clock constraint.

For design constraint in 400kHz,
total leakage power = 2.7uW

For design constraint in 1.1MHz,
total leakage power = 0.7 uW

Can anyone help to explain this? THanks.
Click to expand...


That's seems to me perfectly logical.

You have the same circuits and your are testing them at differents clock speed with the same voltage. The leakage power is the power consumed by the circuit when it is no in switching phase. So the more the clock is quick the more the circuit have activity so the less static power is consumed.
 

Re: Total Leakge Power

That is very interesting view from AdvaRes.

In order to confirm your theory, i need to check the number of low VT cell vs number of high VT cell.

Can anybody guide me how to check that?

Thanks.
 

Re: Total Leakge Power

cafukarfoo said:
That is very interesting view from AdvaRes.

In order to confirm your theory, i need to check the number of low VT cell vs number of high VT cell.

Can anybody guide me how to check that?

Thanks.
Click to expand...

What's your circuit ?
If you have the time and the circuit is not very complex, you can count them manually.
 

Re: Total Leakge Power

It is a SMB/I2C slave circuit + control part.

How can i identify which cell is low VT and high VT?
 

Re: Total Leakge Power

Which CAD tool are you using ?
 

Re: Total Leakge Power

Cadence First Encounter
Synopsys DC & PT
 

Total Leakge Power

Low VT vs high VT cells usually have a different naming convention in your .lib file. You should be able to just grep <vt syntax> <netlist> | wc -l
 

Re: Total Leakge Power

Hello iwpia50s,

I am using TSMC library.

Can you tell me what is the <vt syntax>?

Thanks
 

Re: Total Leakge Power

Hi,

For TSMC lib. e.g. cellX*TL will be low vt, cellX*TH will be high vt and cellX*TR will be regular vt cell.

Or you can also analyze the arc report of the library and comapre the leakage and delays of teh perticular group of cells i.e. high vt and low vt.

It may help you.

Thanks..

HAK..
 

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